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488 lines
12 KiB
488 lines
12 KiB
* Generic Exynos Bus frequency device |
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The Samsung Exynos SoC has many buses for data transfer between DRAM |
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and sub-blocks in SoC. Most Exynos SoCs share the common architecture |
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for buses. Generally, each bus of Exynos SoC includes a source clock |
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and a power line, which are able to change the clock frequency |
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of the bus in runtime. To monitor the usage of each bus in runtime, |
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the driver uses the PPMU (Platform Performance Monitoring Unit), which |
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is able to measure the current load of sub-blocks. |
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The Exynos SoC includes the various sub-blocks which have the each AXI bus. |
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The each AXI bus has the owned source clock but, has not the only owned |
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power line. The power line might be shared among one more sub-blocks. |
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So, we can divide into two type of device as the role of each sub-block. |
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There are two type of bus devices as following: |
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- parent bus device |
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- passive bus device |
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Basically, parent and passive bus device share the same power line. |
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The parent bus device can only change the voltage of shared power line |
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and the rest bus devices (passive bus device) depend on the decision of |
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the parent bus device. If there are three blocks which share the VDD_xxx |
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power line, Only one block should be parent device and then the rest blocks |
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should depend on the parent device as passive device. |
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VDD_xxx |--- A block (parent) |
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|--- B block (passive) |
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|--- C block (passive) |
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There are a little different composition among Exynos SoC because each Exynos |
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SoC has different sub-blocks. Therefore, such difference should be specified |
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in devicetree file instead of each device driver. In result, this driver |
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is able to support the bus frequency for all Exynos SoCs. |
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Required properties for all bus devices: |
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- compatible: Should be "samsung,exynos-bus". |
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- clock-names : the name of clock used by the bus, "bus". |
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- clocks : phandles for clock specified in "clock-names" property. |
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- operating-points-v2: the OPP table including frequency/voltage information |
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to support DVFS (Dynamic Voltage/Frequency Scaling) feature. |
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Required properties only for parent bus device: |
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- vdd-supply: the regulator to provide the buses with the voltage. |
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- devfreq-events: the devfreq-event device to monitor the current utilization |
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of buses. |
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Required properties only for passive bus device: |
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- devfreq: the parent bus device. |
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Optional properties only for parent bus device: |
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- exynos,saturation-ratio: the percentage value which is used to calibrate |
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the performance count against total cycle count. |
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Optional properties for the interconnect functionality (QoS frequency |
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constraints): |
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- #interconnect-cells: should be 0. |
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- interconnects: as documented in ../interconnect.txt, describes a path at the |
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higher level interconnects used by this interconnect provider. |
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If this interconnect provider is directly linked to a top level interconnect |
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provider the property contains only one phandle. The provider extends |
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the interconnect graph by linking its node to a node registered by provider |
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pointed to by first phandle in the 'interconnects' property. |
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- samsung,data-clock-ratio: ratio of the data throughput in B/s to minimum data |
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clock frequency in Hz, default value is 8 when this property is missing. |
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Detailed correlation between sub-blocks and power line according to Exynos SoC: |
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- In case of Exynos3250, there are two power line as following: |
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VDD_MIF |--- DMC |
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VDD_INT |--- LEFTBUS (parent device) |
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|--- PERIL |
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|--- MFC |
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|--- G3D |
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|--- RIGHTBUS |
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|--- PERIR |
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|--- FSYS |
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|--- LCD0 |
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|--- PERIR |
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|--- ISP |
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|--- CAM |
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- In case of Exynos4210, there is one power line as following: |
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VDD_INT |--- DMC (parent device) |
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|--- LEFTBUS |
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|--- PERIL |
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|--- MFC(L) |
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|--- G3D |
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|--- TV |
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|--- LCD0 |
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|--- RIGHTBUS |
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|--- PERIR |
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|--- MFC(R) |
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|--- CAM |
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|--- FSYS |
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|--- GPS |
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|--- LCD0 |
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|--- LCD1 |
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- In case of Exynos4x12, there are two power line as following: |
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VDD_MIF |--- DMC |
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VDD_INT |--- LEFTBUS (parent device) |
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|--- PERIL |
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|--- MFC(L) |
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|--- G3D |
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|--- TV |
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|--- IMAGE |
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|--- RIGHTBUS |
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|--- PERIR |
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|--- MFC(R) |
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|--- CAM |
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|--- FSYS |
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|--- GPS |
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|--- LCD0 |
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|--- ISP |
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- In case of Exynos5422, there are two power line as following: |
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VDD_MIF |--- DREX 0 (parent device, DRAM EXpress controller) |
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|--- DREX 1 |
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VDD_INT |--- NoC_Core (parent device) |
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|--- G2D |
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|--- G3D |
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|--- DISP1 |
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|--- NoC_WCORE |
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|--- GSCL |
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|--- MSCL |
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|--- ISP |
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|--- MFC |
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|--- GEN |
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|--- PERIS |
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|--- PERIC |
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|--- FSYS |
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|--- FSYS2 |
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- In case of Exynos5433, there is VDD_INT power line as following: |
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VDD_INT |--- G2D (parent device) |
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|--- MSCL |
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|--- GSCL |
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|--- JPEG |
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|--- MFC |
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|--- HEVC |
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|--- BUS0 |
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|--- BUS1 |
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|--- BUS2 |
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|--- PERIS (Fixed clock rate) |
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|--- PERIC (Fixed clock rate) |
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|--- FSYS (Fixed clock rate) |
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Example 1: |
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Show the AXI buses of Exynos3250 SoC. Exynos3250 divides the buses to |
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power line (regulator). The MIF (Memory Interface) AXI bus is used to |
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transfer data between DRAM and CPU and uses the VDD_MIF regulator. |
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- MIF (Memory Interface) block |
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: VDD_MIF |--- DMC (Dynamic Memory Controller) |
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- INT (Internal) block |
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: VDD_INT |--- LEFTBUS (parent device) |
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|--- PERIL |
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|--- MFC |
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|--- G3D |
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|--- RIGHTBUS |
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|--- FSYS |
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|--- LCD0 |
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|--- PERIR |
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|--- ISP |
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|--- CAM |
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- MIF bus's frequency/voltage table |
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----------------------- |
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|Lv| Freq | Voltage | |
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----------------------- |
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|L1| 50000 |800000 | |
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|L2| 100000 |800000 | |
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|L3| 134000 |800000 | |
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|L4| 200000 |825000 | |
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|L5| 400000 |875000 | |
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----------------------- |
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- INT bus's frequency/voltage table |
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---------------------------------------------------------- |
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|Block|LEFTBUS|RIGHTBUS|MCUISP |ISP |PERIL ||VDD_INT | |
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| name| |LCD0 | | | || | |
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| | |FSYS | | | || | |
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| | |MFC | | | || | |
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---------------------------------------------------------- |
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|Mode |*parent|passive |passive|passive|passive|| | |
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---------------------------------------------------------- |
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|Lv |Frequency ||Voltage | |
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---------------------------------------------------------- |
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|L1 |50000 |50000 |50000 |50000 |50000 ||900000 | |
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|L2 |80000 |80000 |80000 |80000 |80000 ||900000 | |
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|L3 |100000 |100000 |100000 |100000 |100000 ||1000000 | |
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|L4 |134000 |134000 |200000 |200000 | ||1000000 | |
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|L5 |200000 |200000 |400000 |300000 | ||1000000 | |
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---------------------------------------------------------- |
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Example 2: |
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The bus of DMC (Dynamic Memory Controller) block in exynos3250.dtsi |
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is listed below: |
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bus_dmc: bus_dmc { |
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compatible = "samsung,exynos-bus"; |
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clocks = <&cmu_dmc CLK_DIV_DMC>; |
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clock-names = "bus"; |
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operating-points-v2 = <&bus_dmc_opp_table>; |
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status = "disabled"; |
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}; |
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bus_dmc_opp_table: opp_table1 { |
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compatible = "operating-points-v2"; |
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opp-shared; |
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opp-50000000 { |
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opp-hz = /bits/ 64 <50000000>; |
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opp-microvolt = <800000>; |
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}; |
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opp-100000000 { |
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opp-hz = /bits/ 64 <100000000>; |
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opp-microvolt = <800000>; |
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}; |
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opp-134000000 { |
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opp-hz = /bits/ 64 <134000000>; |
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opp-microvolt = <800000>; |
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}; |
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opp-200000000 { |
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opp-hz = /bits/ 64 <200000000>; |
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opp-microvolt = <825000>; |
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}; |
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opp-400000000 { |
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opp-hz = /bits/ 64 <400000000>; |
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opp-microvolt = <875000>; |
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}; |
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}; |
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bus_leftbus: bus_leftbus { |
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compatible = "samsung,exynos-bus"; |
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clocks = <&cmu CLK_DIV_GDL>; |
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clock-names = "bus"; |
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operating-points-v2 = <&bus_leftbus_opp_table>; |
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status = "disabled"; |
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}; |
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bus_rightbus: bus_rightbus { |
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compatible = "samsung,exynos-bus"; |
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clocks = <&cmu CLK_DIV_GDR>; |
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clock-names = "bus"; |
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operating-points-v2 = <&bus_leftbus_opp_table>; |
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status = "disabled"; |
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}; |
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bus_lcd0: bus_lcd0 { |
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compatible = "samsung,exynos-bus"; |
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clocks = <&cmu CLK_DIV_ACLK_160>; |
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clock-names = "bus"; |
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operating-points-v2 = <&bus_leftbus_opp_table>; |
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status = "disabled"; |
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}; |
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bus_fsys: bus_fsys { |
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compatible = "samsung,exynos-bus"; |
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clocks = <&cmu CLK_DIV_ACLK_200>; |
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clock-names = "bus"; |
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operating-points-v2 = <&bus_leftbus_opp_table>; |
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status = "disabled"; |
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}; |
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bus_mcuisp: bus_mcuisp { |
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compatible = "samsung,exynos-bus"; |
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clocks = <&cmu CLK_DIV_ACLK_400_MCUISP>; |
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clock-names = "bus"; |
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operating-points-v2 = <&bus_mcuisp_opp_table>; |
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status = "disabled"; |
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}; |
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bus_isp: bus_isp { |
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compatible = "samsung,exynos-bus"; |
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clocks = <&cmu CLK_DIV_ACLK_266>; |
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clock-names = "bus"; |
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operating-points-v2 = <&bus_isp_opp_table>; |
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status = "disabled"; |
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}; |
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bus_peril: bus_peril { |
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compatible = "samsung,exynos-bus"; |
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clocks = <&cmu CLK_DIV_ACLK_100>; |
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clock-names = "bus"; |
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operating-points-v2 = <&bus_peril_opp_table>; |
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status = "disabled"; |
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}; |
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bus_mfc: bus_mfc { |
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compatible = "samsung,exynos-bus"; |
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clocks = <&cmu CLK_SCLK_MFC>; |
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clock-names = "bus"; |
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operating-points-v2 = <&bus_leftbus_opp_table>; |
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status = "disabled"; |
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}; |
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bus_leftbus_opp_table: opp_table1 { |
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compatible = "operating-points-v2"; |
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opp-shared; |
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opp-50000000 { |
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opp-hz = /bits/ 64 <50000000>; |
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opp-microvolt = <900000>; |
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}; |
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opp-80000000 { |
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opp-hz = /bits/ 64 <80000000>; |
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opp-microvolt = <900000>; |
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}; |
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opp-100000000 { |
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opp-hz = /bits/ 64 <100000000>; |
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opp-microvolt = <1000000>; |
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}; |
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opp-134000000 { |
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opp-hz = /bits/ 64 <134000000>; |
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opp-microvolt = <1000000>; |
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}; |
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opp-200000000 { |
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opp-hz = /bits/ 64 <200000000>; |
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opp-microvolt = <1000000>; |
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}; |
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}; |
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bus_mcuisp_opp_table: opp_table2 { |
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compatible = "operating-points-v2"; |
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opp-shared; |
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opp-50000000 { |
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opp-hz = /bits/ 64 <50000000>; |
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}; |
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opp-80000000 { |
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opp-hz = /bits/ 64 <80000000>; |
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}; |
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opp-100000000 { |
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opp-hz = /bits/ 64 <100000000>; |
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}; |
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opp-200000000 { |
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opp-hz = /bits/ 64 <200000000>; |
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}; |
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opp-400000000 { |
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opp-hz = /bits/ 64 <400000000>; |
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}; |
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}; |
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bus_isp_opp_table: opp_table3 { |
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compatible = "operating-points-v2"; |
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opp-shared; |
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opp-50000000 { |
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opp-hz = /bits/ 64 <50000000>; |
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}; |
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opp-80000000 { |
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opp-hz = /bits/ 64 <80000000>; |
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}; |
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opp-100000000 { |
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opp-hz = /bits/ 64 <100000000>; |
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}; |
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opp-200000000 { |
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opp-hz = /bits/ 64 <200000000>; |
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}; |
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opp-300000000 { |
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opp-hz = /bits/ 64 <300000000>; |
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}; |
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}; |
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bus_peril_opp_table: opp_table4 { |
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compatible = "operating-points-v2"; |
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opp-shared; |
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opp-50000000 { |
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opp-hz = /bits/ 64 <50000000>; |
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}; |
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opp-80000000 { |
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opp-hz = /bits/ 64 <80000000>; |
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}; |
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opp-100000000 { |
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opp-hz = /bits/ 64 <100000000>; |
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}; |
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}; |
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Usage case to handle the frequency and voltage of bus on runtime |
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in exynos3250-rinato.dts is listed below: |
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&bus_dmc { |
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devfreq-events = <&ppmu_dmc0_3>, <&ppmu_dmc1_3>; |
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vdd-supply = <&buck1_reg>; /* VDD_MIF */ |
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status = "okay"; |
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}; |
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&bus_leftbus { |
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devfreq-events = <&ppmu_leftbus_3>, <&ppmu_rightbus_3>; |
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vdd-supply = <&buck3_reg>; |
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status = "okay"; |
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}; |
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&bus_rightbus { |
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devfreq = <&bus_leftbus>; |
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status = "okay"; |
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}; |
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&bus_lcd0 { |
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devfreq = <&bus_leftbus>; |
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status = "okay"; |
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}; |
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&bus_fsys { |
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devfreq = <&bus_leftbus>; |
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status = "okay"; |
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}; |
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&bus_mcuisp { |
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devfreq = <&bus_leftbus>; |
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status = "okay"; |
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}; |
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&bus_isp { |
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devfreq = <&bus_leftbus>; |
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status = "okay"; |
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}; |
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&bus_peril { |
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devfreq = <&bus_leftbus>; |
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status = "okay"; |
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}; |
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&bus_mfc { |
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devfreq = <&bus_leftbus>; |
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status = "okay"; |
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}; |
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Example 3: |
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An interconnect path "bus_display -- bus_leftbus -- bus_dmc" on |
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Exynos4412 SoC with video mixer as an interconnect consumer device. |
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soc { |
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bus_dmc: bus_dmc { |
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compatible = "samsung,exynos-bus"; |
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clocks = <&clock CLK_DIV_DMC>; |
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clock-names = "bus"; |
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operating-points-v2 = <&bus_dmc_opp_table>; |
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samsung,data-clock-ratio = <4>; |
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#interconnect-cells = <0>; |
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}; |
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bus_leftbus: bus_leftbus { |
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compatible = "samsung,exynos-bus"; |
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clocks = <&clock CLK_DIV_GDL>; |
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clock-names = "bus"; |
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operating-points-v2 = <&bus_leftbus_opp_table>; |
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#interconnect-cells = <0>; |
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interconnects = <&bus_dmc>; |
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}; |
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bus_display: bus_display { |
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compatible = "samsung,exynos-bus"; |
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clocks = <&clock CLK_ACLK160>; |
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clock-names = "bus"; |
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operating-points-v2 = <&bus_display_opp_table>; |
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#interconnect-cells = <0>; |
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interconnects = <&bus_leftbus &bus_dmc>; |
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}; |
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bus_dmc_opp_table: opp_table1 { |
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compatible = "operating-points-v2"; |
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/* ... */ |
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} |
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bus_leftbus_opp_table: opp_table3 { |
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compatible = "operating-points-v2"; |
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/* ... */ |
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}; |
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bus_display_opp_table: opp_table4 { |
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compatible = "operating-points-v2"; |
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/* .. */ |
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}; |
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&mixer { |
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compatible = "samsung,exynos4212-mixer"; |
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interconnects = <&bus_display &bus_dmc>; |
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/* ... */ |
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}; |
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};
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