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40 lines
1.5 KiB
40 lines
1.5 KiB
Inside Secure SafeXcel cryptographic engine |
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Required properties: |
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- compatible: Should be "inside-secure,safexcel-eip197b", |
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"inside-secure,safexcel-eip197d" or |
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"inside-secure,safexcel-eip97ies". |
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- reg: Base physical address of the engine and length of memory mapped region. |
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- interrupts: Interrupt numbers for the rings and engine. |
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- interrupt-names: Should be "ring0", "ring1", "ring2", "ring3", "eip", "mem". |
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Optional properties: |
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- clocks: Reference to the crypto engine clocks, the second clock is |
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needed for the Armada 7K/8K SoCs. |
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- clock-names: mandatory if there is a second clock, in this case the |
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name must be "core" for the first clock and "reg" for |
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the second one. |
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Backward compatibility: |
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Two compatibles are kept for backward compatibility, but shouldn't be used for |
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new submissions: |
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- "inside-secure,safexcel-eip197" is equivalent to |
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"inside-secure,safexcel-eip197b". |
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- "inside-secure,safexcel-eip97" is equivalent to |
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"inside-secure,safexcel-eip97ies". |
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Example: |
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crypto: crypto@800000 { |
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compatible = "inside-secure,safexcel-eip197b"; |
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reg = <0x800000 0x200000>; |
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interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; |
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interrupt-names = "mem", "ring0", "ring1", "ring2", "ring3", |
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"eip"; |
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clocks = <&cpm_syscon0 1 26>; |
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};
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