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553 lines
16 KiB
553 lines
16 KiB
===================================================================== |
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SEC 4 Device Tree Binding |
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Copyright (C) 2008-2011 Freescale Semiconductor Inc. |
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CONTENTS |
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-Overview |
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-SEC 4 Node |
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-Job Ring Node |
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-Run Time Integrity Check (RTIC) Node |
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-Run Time Integrity Check (RTIC) Memory Node |
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-Secure Non-Volatile Storage (SNVS) Node |
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-Secure Non-Volatile Storage (SNVS) Low Power (LP) RTC Node |
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-Full Example |
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NOTE: the SEC 4 is also known as Freescale's Cryptographic Accelerator |
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Accelerator and Assurance Module (CAAM). |
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===================================================================== |
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Overview |
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DESCRIPTION |
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SEC 4 h/w can process requests from 2 types of sources. |
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1. DPAA Queue Interface (HW interface between Queue Manager & SEC 4). |
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2. Job Rings (HW interface between cores & SEC 4 registers). |
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High Speed Data Path Configuration: |
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HW interface between QM & SEC 4 and also BM & SEC 4, on DPAA-enabled parts |
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such as the P4080. The number of simultaneous dequeues the QI can make is |
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equal to the number of Descriptor Controller (DECO) engines in a particular |
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SEC version. E.g., the SEC 4.0 in the P4080 has 5 DECOs and can thus |
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dequeue from 5 subportals simultaneously. |
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Job Ring Data Path Configuration: |
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Each JR is located on a separate 4k page, they may (or may not) be made visible |
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in the memory partition devoted to a particular core. The P4080 has 4 JRs, so |
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up to 4 JRs can be configured; and all 4 JRs process requests in parallel. |
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===================================================================== |
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SEC 4 Node |
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Description |
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Node defines the base address of the SEC 4 block. |
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This block specifies the address range of all global |
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configuration registers for the SEC 4 block. It |
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also receives interrupts from the Run Time Integrity Check |
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(RTIC) function within the SEC 4 block. |
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PROPERTIES |
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- compatible |
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Usage: required |
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Value type: <string> |
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Definition: Must include "fsl,sec-v4.0" |
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- fsl,sec-era |
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Usage: optional |
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Value type: <u32> |
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Definition: A standard property. Define the 'ERA' of the SEC |
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device. |
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- #address-cells |
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Usage: required |
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Value type: <u32> |
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Definition: A standard property. Defines the number of cells |
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for representing physical addresses in child nodes. |
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- #size-cells |
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Usage: required |
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Value type: <u32> |
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Definition: A standard property. Defines the number of cells |
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for representing the size of physical addresses in |
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child nodes. |
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- reg |
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Usage: required |
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Value type: <prop-encoded-array> |
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Definition: A standard property. Specifies the physical |
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address and length of the SEC4 configuration registers. |
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registers |
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- ranges |
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Usage: required |
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Value type: <prop-encoded-array> |
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Definition: A standard property. Specifies the physical address |
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range of the SEC 4.0 register space (-SNVS not included). A |
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triplet that includes the child address, parent address, & |
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length. |
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- interrupts |
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Usage: required |
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Value type: <prop_encoded-array> |
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Definition: Specifies the interrupts generated by this |
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device. The value of the interrupts property |
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consists of one interrupt specifier. The format |
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of the specifier is defined by the binding document |
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describing the node's interrupt parent. |
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- clocks |
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Usage: required if SEC 4.0 requires explicit enablement of clocks |
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Value type: <prop_encoded-array> |
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Definition: A list of phandle and clock specifier pairs describing |
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the clocks required for enabling and disabling SEC 4.0. |
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- clock-names |
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Usage: required if SEC 4.0 requires explicit enablement of clocks |
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Value type: <string> |
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Definition: A list of clock name strings in the same order as the |
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clocks property. |
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Note: All other standard properties (see the Devicetree Specification) |
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are allowed but are optional. |
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EXAMPLE |
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iMX6QDL/SX requires four clocks |
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crypto@300000 { |
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compatible = "fsl,sec-v4.0"; |
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fsl,sec-era = <2>; |
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#address-cells = <1>; |
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#size-cells = <1>; |
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reg = <0x300000 0x10000>; |
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ranges = <0 0x300000 0x10000>; |
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interrupt-parent = <&mpic>; |
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interrupts = <92 2>; |
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clocks = <&clks IMX6QDL_CLK_CAAM_MEM>, |
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<&clks IMX6QDL_CLK_CAAM_ACLK>, |
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<&clks IMX6QDL_CLK_CAAM_IPG>, |
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<&clks IMX6QDL_CLK_EIM_SLOW>; |
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clock-names = "mem", "aclk", "ipg", "emi_slow"; |
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}; |
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iMX6UL does only require three clocks |
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crypto: crypto@2140000 { |
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compatible = "fsl,sec-v4.0"; |
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#address-cells = <1>; |
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#size-cells = <1>; |
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reg = <0x2140000 0x3c000>; |
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ranges = <0 0x2140000 0x3c000>; |
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interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; |
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clocks = <&clks IMX6UL_CLK_CAAM_MEM>, |
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<&clks IMX6UL_CLK_CAAM_ACLK>, |
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<&clks IMX6UL_CLK_CAAM_IPG>; |
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clock-names = "mem", "aclk", "ipg"; |
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}; |
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===================================================================== |
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Job Ring (JR) Node |
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Child of the crypto node defines data processing interface to SEC 4 |
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across the peripheral bus for purposes of processing |
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cryptographic descriptors. The specified address |
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range can be made visible to one (or more) cores. |
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The interrupt defined for this node is controlled within |
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the address range of this node. |
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- compatible |
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Usage: required |
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Value type: <string> |
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Definition: Must include "fsl,sec-v4.0-job-ring" |
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- reg |
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Usage: required |
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Value type: <prop-encoded-array> |
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Definition: Specifies a two JR parameters: an offset from |
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the parent physical address and the length the JR registers. |
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- fsl,liodn |
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Usage: optional-but-recommended |
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Value type: <prop-encoded-array> |
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Definition: |
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Specifies the LIODN to be used in conjunction with |
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the ppid-to-liodn table that specifies the PPID to LIODN mapping. |
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Needed if the PAMU is used. Value is a 12 bit value |
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where value is a LIODN ID for this JR. This property is |
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normally set by boot firmware. |
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- interrupts |
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Usage: required |
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Value type: <prop_encoded-array> |
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Definition: Specifies the interrupts generated by this |
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device. The value of the interrupts property |
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consists of one interrupt specifier. The format |
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of the specifier is defined by the binding document |
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describing the node's interrupt parent. |
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EXAMPLE |
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jr@1000 { |
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compatible = "fsl,sec-v4.0-job-ring"; |
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reg = <0x1000 0x1000>; |
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fsl,liodn = <0x081>; |
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interrupt-parent = <&mpic>; |
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interrupts = <88 2>; |
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}; |
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===================================================================== |
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Run Time Integrity Check (RTIC) Node |
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Child node of the crypto node. Defines a register space that |
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contains up to 5 sets of addresses and their lengths (sizes) that |
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will be checked at run time. After an initial hash result is |
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calculated, these addresses are checked by HW to monitor any |
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change. If any memory is modified, a Security Violation is |
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triggered (see SNVS definition). |
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- compatible |
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Usage: required |
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Value type: <string> |
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Definition: Must include "fsl,sec-v4.0-rtic". |
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- #address-cells |
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Usage: required |
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Value type: <u32> |
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Definition: A standard property. Defines the number of cells |
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for representing physical addresses in child nodes. Must |
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have a value of 1. |
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- #size-cells |
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Usage: required |
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Value type: <u32> |
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Definition: A standard property. Defines the number of cells |
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for representing the size of physical addresses in |
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child nodes. Must have a value of 1. |
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- reg |
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Usage: required |
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Value type: <prop-encoded-array> |
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Definition: A standard property. Specifies a two parameters: |
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an offset from the parent physical address and the length |
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the SEC4 registers. |
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- ranges |
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Usage: required |
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Value type: <prop-encoded-array> |
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Definition: A standard property. Specifies the physical address |
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range of the SEC 4 register space (-SNVS not included). A |
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triplet that includes the child address, parent address, & |
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length. |
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EXAMPLE |
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rtic@6000 { |
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compatible = "fsl,sec-v4.0-rtic"; |
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#address-cells = <1>; |
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#size-cells = <1>; |
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reg = <0x6000 0x100>; |
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ranges = <0x0 0x6100 0xe00>; |
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}; |
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===================================================================== |
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Run Time Integrity Check (RTIC) Memory Node |
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A child node that defines individual RTIC memory regions that are used to |
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perform run-time integrity check of memory areas that should not modified. |
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The node defines a register that contains the memory address & |
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length (combined) and a second register that contains the hash result |
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in big endian format. |
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- compatible |
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Usage: required |
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Value type: <string> |
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Definition: Must include "fsl,sec-v4.0-rtic-memory". |
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- reg |
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Usage: required |
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Value type: <prop-encoded-array> |
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Definition: A standard property. Specifies two parameters: |
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an offset from the parent physical address and the length: |
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1. The location of the RTIC memory address & length registers. |
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2. The location RTIC hash result. |
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- fsl,rtic-region |
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Usage: optional-but-recommended |
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Value type: <prop-encoded-array> |
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Definition: |
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Specifies the HW address (36 bit address) for this region |
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followed by the length of the HW partition to be checked; |
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the address is represented as a 64 bit quantity followed |
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by a 32 bit length. |
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- fsl,liodn |
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Usage: optional-but-recommended |
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Value type: <prop-encoded-array> |
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Definition: |
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Specifies the LIODN to be used in conjunction with |
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the ppid-to-liodn table that specifies the PPID to LIODN |
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mapping. Needed if the PAMU is used. Value is a 12 bit value |
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where value is a LIODN ID for this RTIC memory region. This |
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property is normally set by boot firmware. |
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EXAMPLE |
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rtic-a@0 { |
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compatible = "fsl,sec-v4.0-rtic-memory"; |
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reg = <0x00 0x20 0x100 0x80>; |
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fsl,liodn = <0x03c>; |
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fsl,rtic-region = <0x12345678 0x12345678 0x12345678>; |
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}; |
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===================================================================== |
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Secure Non-Volatile Storage (SNVS) Node |
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Node defines address range and the associated |
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interrupt for the SNVS function. This function |
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monitors security state information & reports |
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security violations. This also included rtc, |
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system power off and ON/OFF key. |
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- compatible |
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Usage: required |
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Value type: <string> |
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Definition: Must include "fsl,sec-v4.0-mon" and "syscon". |
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- reg |
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Usage: required |
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Value type: <prop-encoded-array> |
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Definition: A standard property. Specifies the physical |
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address and length of the SEC4 configuration |
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registers. |
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- #address-cells |
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Usage: required |
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Value type: <u32> |
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Definition: A standard property. Defines the number of cells |
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for representing physical addresses in child nodes. Must |
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have a value of 1. |
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- #size-cells |
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Usage: required |
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Value type: <u32> |
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Definition: A standard property. Defines the number of cells |
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for representing the size of physical addresses in |
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child nodes. Must have a value of 1. |
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- ranges |
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Usage: required |
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Value type: <prop-encoded-array> |
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Definition: A standard property. Specifies the physical address |
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range of the SNVS register space. A triplet that includes |
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the child address, parent address, & length. |
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- interrupts |
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Usage: optional |
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Value type: <prop_encoded-array> |
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Definition: Specifies the interrupts generated by this |
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device. The value of the interrupts property |
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consists of one interrupt specifier. The format |
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of the specifier is defined by the binding document |
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describing the node's interrupt parent. |
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EXAMPLE |
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sec_mon@314000 { |
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compatible = "fsl,sec-v4.0-mon", "syscon"; |
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reg = <0x314000 0x1000>; |
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ranges = <0 0x314000 0x1000>; |
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interrupt-parent = <&mpic>; |
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interrupts = <93 2>; |
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}; |
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===================================================================== |
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Secure Non-Volatile Storage (SNVS) Low Power (LP) RTC Node |
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A SNVS child node that defines SNVS LP RTC. |
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- compatible |
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Usage: required |
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Value type: <string> |
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Definition: Must include "fsl,sec-v4.0-mon-rtc-lp". |
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- interrupts |
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Usage: required |
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Value type: <prop_encoded-array> |
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Definition: Specifies the interrupts generated by this |
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device. The value of the interrupts property |
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consists of one interrupt specifier. The format |
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of the specifier is defined by the binding document |
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describing the node's interrupt parent. |
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- regmap |
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Usage: required |
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Value type: <phandle> |
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Definition: this is phandle to the register map node. |
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- offset |
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Usage: option |
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value type: <u32> |
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Definition: LP register offset. default it is 0x34. |
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- clocks |
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Usage: optional, required if SNVS LP RTC requires explicit |
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enablement of clocks |
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Value type: <prop_encoded-array> |
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Definition: a clock specifier describing the clock required for |
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enabling and disabling SNVS LP RTC. |
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- clock-names |
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Usage: optional, required if SNVS LP RTC requires explicit |
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enablement of clocks |
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Value type: <string> |
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Definition: clock name string should be "snvs-rtc". |
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EXAMPLE |
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sec_mon_rtc_lp@1 { |
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compatible = "fsl,sec-v4.0-mon-rtc-lp"; |
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interrupts = <93 2>; |
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regmap = <&snvs>; |
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offset = <0x34>; |
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clocks = <&clks IMX7D_SNVS_CLK>; |
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clock-names = "snvs-rtc"; |
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}; |
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===================================================================== |
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System ON/OFF key driver |
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The snvs-pwrkey is designed to enable POWER key function which controlled |
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by SNVS ONOFF, the driver can report the status of POWER key and wakeup |
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system if pressed after system suspend. |
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- compatible: |
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Usage: required |
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Value type: <string> |
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Definition: Mush include "fsl,sec-v4.0-pwrkey". |
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- interrupts: |
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Usage: required |
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Value type: <prop_encoded-array> |
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Definition: The SNVS ON/OFF interrupt number to the CPU(s). |
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- linux,keycode: |
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Usage: option |
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Value type: <int> |
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Definition: Keycode to emit, KEY_POWER by default. |
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- wakeup-source: |
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Usage: option |
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Value type: <boo> |
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Definition: Button can wake-up the system. |
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- regmap: |
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Usage: required: |
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Value type: <phandle> |
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Definition: this is phandle to the register map node. |
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EXAMPLE: |
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snvs-pwrkey@020cc000 { |
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compatible = "fsl,sec-v4.0-pwrkey"; |
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regmap = <&snvs>; |
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interrupts = <0 4 0x4> |
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linux,keycode = <116>; /* KEY_POWER */ |
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wakeup-source; |
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}; |
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===================================================================== |
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FULL EXAMPLE |
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crypto: crypto@300000 { |
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compatible = "fsl,sec-v4.0"; |
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#address-cells = <1>; |
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#size-cells = <1>; |
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reg = <0x300000 0x10000>; |
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ranges = <0 0x300000 0x10000>; |
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interrupt-parent = <&mpic>; |
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interrupts = <92 2>; |
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sec_jr0: jr@1000 { |
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compatible = "fsl,sec-v4.0-job-ring"; |
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reg = <0x1000 0x1000>; |
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interrupt-parent = <&mpic>; |
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interrupts = <88 2>; |
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}; |
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sec_jr1: jr@2000 { |
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compatible = "fsl,sec-v4.0-job-ring"; |
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reg = <0x2000 0x1000>; |
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interrupt-parent = <&mpic>; |
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interrupts = <89 2>; |
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}; |
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sec_jr2: jr@3000 { |
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compatible = "fsl,sec-v4.0-job-ring"; |
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reg = <0x3000 0x1000>; |
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interrupt-parent = <&mpic>; |
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interrupts = <90 2>; |
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}; |
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sec_jr3: jr@4000 { |
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compatible = "fsl,sec-v4.0-job-ring"; |
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reg = <0x4000 0x1000>; |
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interrupt-parent = <&mpic>; |
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interrupts = <91 2>; |
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}; |
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rtic@6000 { |
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compatible = "fsl,sec-v4.0-rtic"; |
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#address-cells = <1>; |
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#size-cells = <1>; |
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reg = <0x6000 0x100>; |
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ranges = <0x0 0x6100 0xe00>; |
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rtic_a: rtic-a@0 { |
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compatible = "fsl,sec-v4.0-rtic-memory"; |
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reg = <0x00 0x20 0x100 0x80>; |
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}; |
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rtic_b: rtic-b@20 { |
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compatible = "fsl,sec-v4.0-rtic-memory"; |
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reg = <0x20 0x20 0x200 0x80>; |
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}; |
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rtic_c: rtic-c@40 { |
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compatible = "fsl,sec-v4.0-rtic-memory"; |
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reg = <0x40 0x20 0x300 0x80>; |
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}; |
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rtic_d: rtic-d@60 { |
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compatible = "fsl,sec-v4.0-rtic-memory"; |
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reg = <0x60 0x20 0x500 0x80>; |
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}; |
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}; |
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}; |
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sec_mon: sec_mon@314000 { |
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compatible = "fsl,sec-v4.0-mon"; |
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reg = <0x314000 0x1000>; |
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ranges = <0 0x314000 0x1000>; |
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sec_mon_rtc_lp@34 { |
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compatible = "fsl,sec-v4.0-mon-rtc-lp"; |
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regmap = <&sec_mon>; |
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offset = <0x34>; |
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interrupts = <93 2>; |
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clocks = <&clks IMX7D_SNVS_CLK>; |
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clock-names = "snvs-rtc"; |
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}; |
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snvs-pwrkey@020cc000 { |
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compatible = "fsl,sec-v4.0-pwrkey"; |
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regmap = <&sec_mon>; |
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interrupts = <0 4 0x4>; |
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linux,keycode = <116>; /* KEY_POWER */ |
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wakeup-source; |
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}; |
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}; |
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=====================================================================
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