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110 lines
2.9 KiB
110 lines
2.9 KiB
Device Tree Clock bindings for the Zynq 7000 EPP |
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The Zynq EPP has several different clk providers, each with there own bindings. |
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The purpose of this document is to document their usage. |
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See clock_bindings.txt for more information on the generic clock bindings. |
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See Chapter 25 of Zynq TRM for more information about Zynq clocks. |
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== Clock Controller == |
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The clock controller is a logical abstraction of Zynq's clock tree. It reads |
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required input clock frequencies from the devicetree and acts as clock provider |
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for all clock consumers of PS clocks. |
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Required properties: |
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- #clock-cells : Must be 1 |
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- compatible : "xlnx,ps7-clkc" |
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- reg : SLCR offset and size taken via syscon < 0x100 0x100 > |
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- ps-clk-frequency : Frequency of the oscillator providing ps_clk in HZ |
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(usually 33 MHz oscillators are used for Zynq platforms) |
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- clock-output-names : List of strings used to name the clock outputs. Shall be |
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a list of the outputs given below. |
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Optional properties: |
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- clocks : as described in the clock bindings |
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- clock-names : as described in the clock bindings |
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- fclk-enable : Bit mask to enable FCLKs statically at boot time. |
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Bit [0..3] correspond to FCLK0..FCLK3. The corresponding |
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FCLK will only be enabled if it is actually running at |
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boot time. |
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Clock inputs: |
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The following strings are optional parameters to the 'clock-names' property in |
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order to provide an optional (E)MIO clock source. |
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- swdt_ext_clk |
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- gem0_emio_clk |
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- gem1_emio_clk |
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- mio_clk_XX # with XX = 00..53 |
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... |
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Clock outputs: |
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0: armpll |
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1: ddrpll |
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2: iopll |
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3: cpu_6or4x |
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4: cpu_3or2x |
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5: cpu_2x |
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6: cpu_1x |
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7: ddr2x |
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8: ddr3x |
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9: dci |
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10: lqspi |
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11: smc |
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12: pcap |
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13: gem0 |
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14: gem1 |
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15: fclk0 |
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16: fclk1 |
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17: fclk2 |
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18: fclk3 |
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19: can0 |
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20: can1 |
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21: sdio0 |
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22: sdio1 |
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23: uart0 |
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24: uart1 |
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25: spi0 |
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26: spi1 |
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27: dma |
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28: usb0_aper |
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29: usb1_aper |
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30: gem0_aper |
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31: gem1_aper |
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32: sdio0_aper |
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33: sdio1_aper |
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34: spi0_aper |
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35: spi1_aper |
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36: can0_aper |
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37: can1_aper |
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38: i2c0_aper |
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39: i2c1_aper |
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40: uart0_aper |
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41: uart1_aper |
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42: gpio_aper |
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43: lqspi_aper |
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44: smc_aper |
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45: swdt |
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46: dbg_trc |
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47: dbg_apb |
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Example: |
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clkc: clkc@100 { |
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#clock-cells = <1>; |
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compatible = "xlnx,ps7-clkc"; |
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ps-clk-frequency = <33333333>; |
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reg = <0x100 0x100>; |
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clock-output-names = "armpll", "ddrpll", "iopll", "cpu_6or4x", |
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"cpu_3or2x", "cpu_2x", "cpu_1x", "ddr2x", "ddr3x", |
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"dci", "lqspi", "smc", "pcap", "gem0", "gem1", |
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"fclk0", "fclk1", "fclk2", "fclk3", "can0", "can1", |
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"sdio0", "sdio1", "uart0", "uart1", "spi0", "spi1", |
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"dma", "usb0_aper", "usb1_aper", "gem0_aper", |
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"gem1_aper", "sdio0_aper", "sdio1_aper", |
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"spi0_aper", "spi1_aper", "can0_aper", "can1_aper", |
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"i2c0_aper", "i2c1_aper", "uart0_aper", "uart1_aper", |
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"gpio_aper", "lqspi_aper", "smc_aper", "swdt", |
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"dbg_trc", "dbg_apb"; |
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# optional props |
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clocks = <&clkc 16>, <&clk_foo>; |
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clock-names = "gem1_emio_clk", "can_mio_clk_23"; |
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};
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