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131 lines
4.3 KiB
131 lines
4.3 KiB
Device Tree Clock bindings for APM X-Gene |
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This binding uses the common clock binding[1]. |
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[1] Documentation/devicetree/bindings/clock/clock-bindings.txt |
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Required properties: |
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- compatible : shall be one of the following: |
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"apm,xgene-socpll-clock" - for a X-Gene SoC PLL clock |
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"apm,xgene-pcppll-clock" - for a X-Gene PCP PLL clock |
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"apm,xgene-pmd-clock" - for a X-Gene PMD clock |
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"apm,xgene-device-clock" - for a X-Gene device clock |
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"apm,xgene-socpll-v2-clock" - for a X-Gene SoC PLL v2 clock |
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"apm,xgene-pcppll-v2-clock" - for a X-Gene PCP PLL v2 clock |
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Required properties for SoC or PCP PLL clocks: |
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- reg : shall be the physical PLL register address for the pll clock. |
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- clocks : shall be the input parent clock phandle for the clock. This should |
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be the reference clock. |
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- #clock-cells : shall be set to 1. |
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- clock-output-names : shall be the name of the PLL referenced by derive |
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clock. |
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Optional properties for PLL clocks: |
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- clock-names : shall be the name of the PLL. If missing, use the device name. |
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Required properties for PMD clocks: |
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- reg : shall be the physical register address for the pmd clock. |
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- clocks : shall be the input parent clock phandle for the clock. |
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- #clock-cells : shall be set to 1. |
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- clock-output-names : shall be the name of the clock referenced by derive |
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clock. |
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Optional properties for PLL clocks: |
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- clock-names : shall be the name of the clock. If missing, use the device name. |
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Required properties for device clocks: |
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- reg : shall be a list of address and length pairs describing the CSR |
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reset and/or the divider. Either may be omitted, but at least |
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one must be present. |
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- reg-names : shall be a string list describing the reg resource. This |
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may include "csr-reg" and/or "div-reg". If this property |
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is not present, the reg property is assumed to describe |
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only "csr-reg". |
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- clocks : shall be the input parent clock phandle for the clock. |
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- #clock-cells : shall be set to 1. |
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- clock-output-names : shall be the name of the device referenced. |
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Optional properties for device clocks: |
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- clock-names : shall be the name of the device clock. If missing, use the |
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device name. |
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- csr-offset : Offset to the CSR reset register from the reset address base. |
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Default is 0. |
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- csr-mask : CSR reset mask bit. Default is 0xF. |
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- enable-offset : Offset to the enable register from the reset address base. |
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Default is 0x8. |
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- enable-mask : CSR enable mask bit. Default is 0xF. |
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- divider-offset : Offset to the divider CSR register from the divider base. |
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Default is 0x0. |
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- divider-width : Width of the divider register. Default is 0. |
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- divider-shift : Bit shift of the divider register. Default is 0. |
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For example: |
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pcppll: pcppll@17000100 { |
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compatible = "apm,xgene-pcppll-clock"; |
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#clock-cells = <1>; |
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clocks = <&refclk 0>; |
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clock-names = "pcppll"; |
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reg = <0x0 0x17000100 0x0 0x1000>; |
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clock-output-names = "pcppll"; |
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type = <0>; |
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}; |
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pmd0clk: pmd0clk@7e200200 { |
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compatible = "apm,xgene-pmd-clock"; |
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#clock-cells = <1>; |
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clocks = <&pmdpll 0>; |
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reg = <0x0 0x7e200200 0x0 0x10>; |
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clock-output-names = "pmd0clk"; |
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}; |
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socpll: socpll@17000120 { |
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compatible = "apm,xgene-socpll-clock"; |
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#clock-cells = <1>; |
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clocks = <&refclk 0>; |
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clock-names = "socpll"; |
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reg = <0x0 0x17000120 0x0 0x1000>; |
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clock-output-names = "socpll"; |
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type = <1>; |
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}; |
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qmlclk: qmlclk { |
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compatible = "apm,xgene-device-clock"; |
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#clock-cells = <1>; |
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clocks = <&socplldiv2 0>; |
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clock-names = "qmlclk"; |
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reg = <0x0 0x1703C000 0x0 0x1000>; |
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reg-name = "csr-reg"; |
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clock-output-names = "qmlclk"; |
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}; |
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ethclk: ethclk { |
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compatible = "apm,xgene-device-clock"; |
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#clock-cells = <1>; |
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clocks = <&socplldiv2 0>; |
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clock-names = "ethclk"; |
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reg = <0x0 0x17000000 0x0 0x1000>; |
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reg-names = "div-reg"; |
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divider-offset = <0x238>; |
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divider-width = <0x9>; |
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divider-shift = <0x0>; |
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clock-output-names = "ethclk"; |
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}; |
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apbclk: apbclk { |
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compatible = "apm,xgene-device-clock"; |
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#clock-cells = <1>; |
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clocks = <&ahbclk 0>; |
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clock-names = "apbclk"; |
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reg = <0x0 0x1F2AC000 0x0 0x1000 |
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0x0 0x1F2AC000 0x0 0x1000>; |
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reg-names = "csr-reg", "div-reg"; |
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csr-offset = <0x0>; |
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csr-mask = <0x200>; |
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enable-offset = <0x8>; |
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enable-mask = <0x200>; |
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divider-offset = <0x10>; |
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divider-width = <0x2>; |
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divider-shift = <0x0>; |
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flags = <0x8>; |
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clock-output-names = "apbclk"; |
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}; |
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