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53 lines
1.7 KiB
53 lines
1.7 KiB
Binding for TI CDCE913/925/937/949 programmable I2C clock synthesizers. |
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Reference |
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This binding uses the common clock binding[1]. |
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[1] Documentation/devicetree/bindings/clock/clock-bindings.txt |
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[2] https://www.ti.com/product/cdce913 |
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[3] https://www.ti.com/product/cdce925 |
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[4] https://www.ti.com/product/cdce937 |
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[5] https://www.ti.com/product/cdce949 |
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The driver provides clock sources for each output Y1 through Y5. |
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Required properties: |
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- compatible: Shall be one of the following: |
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- "ti,cdce913": 1-PLL, 3 Outputs |
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- "ti,cdce925": 2-PLL, 5 Outputs |
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- "ti,cdce937": 3-PLL, 7 Outputs |
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- "ti,cdce949": 4-PLL, 9 Outputs |
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- reg: I2C device address. |
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- clocks: Points to a fixed parent clock that provides the input frequency. |
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- #clock-cells: From common clock bindings: Shall be 1. |
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Optional properties: |
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- xtal-load-pf: Crystal load-capacitor value to fine-tune performance on a |
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board, or to compensate for external influences. |
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- vdd-supply: A regulator node for Vdd |
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- vddout-supply: A regulator node for Vddout |
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For all PLL1, PLL2, ... an optional child node can be used to specify spread |
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spectrum clocking parameters for a board. |
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- spread-spectrum: SSC mode as defined in the data sheet. |
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- spread-spectrum-center: Use "centered" mode instead of "max" mode. When |
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present, the clock runs at the requested frequency on average. Otherwise |
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the requested frequency is the maximum value of the SCC range. |
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Example: |
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clockgen: cdce925pw@64 { |
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compatible = "cdce925"; |
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reg = <0x64>; |
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clocks = <&xtal_27Mhz>; |
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#clock-cells = <1>; |
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xtal-load-pf = <5>; |
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vdd-supply = <&1v8-reg>; |
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vddout-supply = <&3v3-reg>; |
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/* PLL options to get SSC 1% centered */ |
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PLL2 { |
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spread-spectrum = <4>; |
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spread-spectrum-center; |
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}; |
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};
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