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138 lines
3.7 KiB
138 lines
3.7 KiB
STMicroelectronics STM32 Reset and Clock Controller |
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The RCC IP is both a reset and a clock controller. |
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Please refer to clock-bindings.txt for common clock controller binding usage. |
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Please also refer to reset.txt for common reset controller binding usage. |
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Required properties: |
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- compatible: Should be: |
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"st,stm32f42xx-rcc" |
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"st,stm32f469-rcc" |
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"st,stm32f746-rcc" |
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"st,stm32f769-rcc" |
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- reg: should be register base and length as documented in the |
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datasheet |
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- #reset-cells: 1, see below |
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- #clock-cells: 2, device nodes should specify the clock in their "clocks" |
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property, containing a phandle to the clock device node, an index selecting |
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between gated clocks and other clocks and an index specifying the clock to |
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use. |
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- clocks: External oscillator clock phandle |
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- high speed external clock signal (HSE) |
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- external I2S clock (I2S_CKIN) |
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Example: |
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rcc: rcc@40023800 { |
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#reset-cells = <1>; |
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#clock-cells = <2> |
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compatible = "st,stm32f42xx-rcc", "st,stm32-rcc"; |
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reg = <0x40023800 0x400>; |
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clocks = <&clk_hse>, <&clk_i2s_ckin>; |
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}; |
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Specifying gated clocks |
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======================= |
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The primary index must be set to 0. |
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The secondary index is the bit number within the RCC register bank, starting |
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from the first RCC clock enable register (RCC_AHB1ENR, address offset 0x30). |
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It is calculated as: index = register_offset / 4 * 32 + bit_offset. |
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Where bit_offset is the bit offset within the register (LSB is 0, MSB is 31). |
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To simplify the usage and to share bit definition with the reset and clock |
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drivers of the RCC IP, macros are available to generate the index in |
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human-readble format. |
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For STM32F4 series, the macro are available here: |
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- include/dt-bindings/mfd/stm32f4-rcc.h |
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Example: |
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/* Gated clock, AHB1 bit 0 (GPIOA) */ |
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... { |
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clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOA)> |
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}; |
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/* Gated clock, AHB2 bit 4 (CRYP) */ |
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... { |
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clocks = <&rcc 0 STM32F4_AHB2_CLOCK(CRYP)> |
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}; |
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Specifying other clocks |
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======================= |
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The primary index must be set to 1. |
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The secondary index is bound with the following magic numbers: |
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0 SYSTICK |
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1 FCLK |
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2 CLK_LSI (low-power clock source) |
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3 CLK_LSE (generated from a 32.768 kHz low-speed external |
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crystal or ceramic resonator) |
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4 CLK_HSE_RTC (HSE division factor for RTC clock) |
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5 CLK_RTC (real-time clock) |
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6 PLL_VCO_I2S (vco frequency of I2S pll) |
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7 PLL_VCO_SAI (vco frequency of SAI pll) |
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8 CLK_LCD (LCD-TFT) |
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9 CLK_I2S (I2S clocks) |
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10 CLK_SAI1 (audio clocks) |
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11 CLK_SAI2 |
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12 CLK_I2SQ_PDIV (post divisor of pll i2s q divisor) |
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13 CLK_SAIQ_PDIV (post divisor of pll sai q divisor) |
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14 CLK_HSI (Internal ocscillator clock) |
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15 CLK_SYSCLK (System Clock) |
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16 CLK_HDMI_CEC (HDMI-CEC clock) |
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17 CLK_SPDIF (SPDIF-Rx clock) |
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18 CLK_USART1 (U(s)arts clocks) |
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19 CLK_USART2 |
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20 CLK_USART3 |
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21 CLK_UART4 |
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22 CLK_UART5 |
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23 CLK_USART6 |
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24 CLK_UART7 |
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25 CLK_UART8 |
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26 CLK_I2C1 (I2S clocks) |
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27 CLK_I2C2 |
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28 CLK_I2C3 |
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29 CLK_I2C4 |
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30 CLK_LPTIMER (LPTimer1 clock) |
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31 CLK_PLL_SRC |
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32 CLK_DFSDM1 |
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33 CLK_ADFSDM1 |
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34 CLK_F769_DSI |
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) |
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Example: |
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/* Misc clock, FCLK */ |
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... { |
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clocks = <&rcc 1 STM32F4_APB1_CLOCK(TIM2)> |
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}; |
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Specifying softreset control of devices |
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======================================= |
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Device nodes should specify the reset channel required in their "resets" |
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property, containing a phandle to the reset device node and an index specifying |
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which channel to use. |
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The index is the bit number within the RCC registers bank, starting from RCC |
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base address. |
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It is calculated as: index = register_offset / 4 * 32 + bit_offset. |
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Where bit_offset is the bit offset within the register. |
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For example, for CRC reset: |
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crc = AHB1RSTR_offset / 4 * 32 + CRCRST_bit_offset = 0x10 / 4 * 32 + 12 = 140 |
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example: |
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timer2 { |
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resets = <&rcc STM32F4_APB1_RESET(TIM2)>; |
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};
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