mirror of https://github.com/Qortal/Brooklyn
You can not select more than 25 topics
Topics must start with a letter or number, can include dashes ('-') and can be up to 35 characters long.
87 lines
3.2 KiB
87 lines
3.2 KiB
* Core Clock bindings for Marvell MVEBU SoCs |
|
|
|
Marvell MVEBU SoCs usually allow to determine core clock frequencies by |
|
reading the Sample-At-Reset (SAR) register. The core clock consumer should |
|
specify the desired clock by having the clock ID in its "clocks" phandle cell. |
|
|
|
The following is a list of provided IDs and clock names on Armada 370/XP: |
|
0 = tclk (Internal Bus clock) |
|
1 = cpuclk (CPU clock) |
|
2 = nbclk (L2 Cache clock) |
|
3 = hclk (DRAM control clock) |
|
4 = dramclk (DDR clock) |
|
|
|
The following is a list of provided IDs and clock names on Armada 375: |
|
0 = tclk (Internal Bus clock) |
|
1 = cpuclk (CPU clock) |
|
2 = l2clk (L2 Cache clock) |
|
3 = ddrclk (DDR clock) |
|
|
|
The following is a list of provided IDs and clock names on Armada 380/385: |
|
0 = tclk (Internal Bus clock) |
|
1 = cpuclk (CPU clock) |
|
2 = l2clk (L2 Cache clock) |
|
3 = ddrclk (DDR clock) |
|
|
|
The following is a list of provided IDs and clock names on Armada 39x: |
|
0 = tclk (Internal Bus clock) |
|
1 = cpuclk (CPU clock) |
|
2 = nbclk (Coherent Fabric clock) |
|
3 = hclk (SDRAM Controller Internal Clock) |
|
4 = dclk (SDRAM Interface Clock) |
|
5 = refclk (Reference Clock) |
|
|
|
The following is a list of provided IDs and clock names on 98dx3236: |
|
0 = tclk (Internal Bus clock) |
|
1 = cpuclk (CPU clock) |
|
2 = ddrclk (DDR clock) |
|
3 = mpll (MPLL Clock) |
|
|
|
The following is a list of provided IDs and clock names on Kirkwood and Dove: |
|
0 = tclk (Internal Bus clock) |
|
1 = cpuclk (CPU0 clock) |
|
2 = l2clk (L2 Cache clock derived from CPU0 clock) |
|
3 = ddrclk (DDR controller clock derived from CPU0 clock) |
|
|
|
The following is a list of provided IDs and clock names on Orion5x: |
|
0 = tclk (Internal Bus clock) |
|
1 = cpuclk (CPU0 clock) |
|
2 = ddrclk (DDR controller clock derived from CPU0 clock) |
|
|
|
Required properties: |
|
- compatible : shall be one of the following: |
|
"marvell,armada-370-core-clock" - For Armada 370 SoC core clocks |
|
"marvell,armada-375-core-clock" - For Armada 375 SoC core clocks |
|
"marvell,armada-380-core-clock" - For Armada 380/385 SoC core clocks |
|
"marvell,armada-390-core-clock" - For Armada 39x SoC core clocks |
|
"marvell,armada-xp-core-clock" - For Armada XP SoC core clocks |
|
"marvell,mv98dx3236-core-clock" - For 98dx3236 family SoC core clocks |
|
"marvell,dove-core-clock" - for Dove SoC core clocks |
|
"marvell,kirkwood-core-clock" - for Kirkwood SoC (except mv88f6180) |
|
"marvell,mv88f6180-core-clock" - for Kirkwood MV88f6180 SoC |
|
"marvell,mv98dx1135-core-clock" - for Kirkwood 98dx1135 SoC |
|
"marvell,mv88f5181-core-clock" - for Orion MV88F5181 SoC |
|
"marvell,mv88f5182-core-clock" - for Orion MV88F5182 SoC |
|
"marvell,mv88f5281-core-clock" - for Orion MV88F5281 SoC |
|
"marvell,mv88f6183-core-clock" - for Orion MV88F6183 SoC |
|
- reg : shall be the register address of the Sample-At-Reset (SAR) register |
|
- #clock-cells : from common clock binding; shall be set to 1 |
|
|
|
Optional properties: |
|
- clock-output-names : from common clock binding; allows overwrite default clock |
|
output names ("tclk", "cpuclk", "l2clk", "ddrclk") |
|
|
|
Example: |
|
|
|
core_clk: core-clocks@d0214 { |
|
compatible = "marvell,dove-core-clock"; |
|
reg = <0xd0214 0x4>; |
|
#clock-cells = <1>; |
|
}; |
|
|
|
spi0: spi@10600 { |
|
compatible = "marvell,orion-spi"; |
|
/* ... */ |
|
/* get tclk from core clock provider */ |
|
clocks = <&core_clk 0>; |
|
};
|
|
|