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59 lines
1.5 KiB
59 lines
1.5 KiB
Devicetree bindings for Maxim MAX9485 Programmable Audio Clock Generator |
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This device exposes 4 clocks in total: |
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- MAX9485_MCLKOUT: A gated, buffered output of the input clock of 27 MHz |
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- MAX9485_CLKOUT: A PLL that can be configured to 16 different discrete |
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frequencies |
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- MAX9485_CLKOUT[1,2]: Two gated outputs for MAX9485_CLKOUT |
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MAX9485_CLKOUT[1,2] are children of MAX9485_CLKOUT which upchain all rate set |
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requests. |
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Required properties: |
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- compatible: "maxim,max9485" |
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- clocks: Input clock, must provice 27.000 MHz |
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- clock-names: Must be set to "xclk" |
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- #clock-cells: From common clock binding; shall be set to 1 |
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Optional properties: |
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- reset-gpios: GPIO descriptor connected to the #RESET input pin |
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- vdd-supply: A regulator node for Vdd |
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- clock-output-names: Name of output clocks, as defined in common clock |
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bindings |
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If not explicitly set, the output names are "mclkout", "clkout", "clkout1" |
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and "clkout2". |
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Clocks are defined as preprocessor macros in the dt-binding header. |
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Example: |
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#include <dt-bindings/clock/maxim,max9485.h> |
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xo-27mhz: xo-27mhz { |
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compatible = "fixed-clock"; |
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#clock-cells = <0>; |
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clock-frequency = <27000000>; |
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}; |
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&i2c0 { |
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max9485: audio-clock@63 { |
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reg = <0x63>; |
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compatible = "maxim,max9485"; |
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clock-names = "xclk"; |
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clocks = <&xo-27mhz>; |
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reset-gpios = <&gpio 1 GPIO_ACTIVE_HIGH>; |
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vdd-supply = <&3v3-reg>; |
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#clock-cells = <1>; |
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}; |
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}; |
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// Clock consumer node |
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foo@0 { |
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compatible = "bar,foo"; |
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/* ... */ |
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clock-names = "foo-input-clk"; |
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clocks = <&max9485 MAX9485_CLKOUT1>; |
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};
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