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52 lines
1.3 KiB
52 lines
1.3 KiB
* NXP LPC1850 CREG clocks |
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The NXP LPC18xx/43xx CREG (Configuration Registers) block contains |
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control registers for two low speed clocks. One of the clocks is a |
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32 kHz oscillator driver with power up/down and clock gating. Next |
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is a fixed divider that creates a 1 kHz clock from the 32 kHz osc. |
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These clocks are used by the RTC and the Event Router peripherials. |
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The 32 kHz can also be routed to other peripherials to enable low |
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power modes. |
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This binding uses the common clock binding: |
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Documentation/devicetree/bindings/clock/clock-bindings.txt |
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Required properties: |
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- compatible: |
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Should be "nxp,lpc1850-creg-clk" |
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- #clock-cells: |
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Shall have value <1>. |
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- clocks: |
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Shall contain a phandle to the fixed 32 kHz crystal. |
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The creg-clk node must be a child of the creg syscon node. |
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The following clocks are available from the clock node. |
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Clock ID Name |
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0 1 kHz clock |
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1 32 kHz Oscillator |
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Example: |
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soc { |
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creg: syscon@40043000 { |
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compatible = "nxp,lpc1850-creg", "syscon", "simple-mfd"; |
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reg = <0x40043000 0x1000>; |
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creg_clk: clock-controller { |
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compatible = "nxp,lpc1850-creg-clk"; |
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clocks = <&xtal32>; |
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#clock-cells = <1>; |
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}; |
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... |
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}; |
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rtc: rtc@40046000 { |
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... |
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clocks = <&creg_clk 0>, <&ccu1 CLK_CPU_BUS>; |
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clock-names = "rtc", "reg"; |
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... |
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}; |
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};
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