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114 lines
3.3 KiB
114 lines
3.3 KiB
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) |
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%YAML 1.2 |
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--- |
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$id: http://devicetree.org/schemas/clock/imx8qxp-lpcg.yaml# |
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$schema: http://devicetree.org/meta-schemas/core.yaml# |
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title: NXP i.MX8QXP LPCG (Low-Power Clock Gating) Clock bindings |
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maintainers: |
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- Aisheng Dong <[email protected]> |
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description: | |
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The Low-Power Clock Gate (LPCG) modules contain a local programming |
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model to control the clock gates for the peripherals. An LPCG module |
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is used to locally gate the clocks for the associated peripheral. |
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This level of clock gating is provided after the clocks are generated |
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by the SCU resources and clock controls. Thus even if the clock is |
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enabled by these control bits, it might still not be running based |
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on the base resource. |
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The clock consumer should specify the desired clock by having the clock |
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ID in its "clocks" phandle cell. See the full list of clock IDs from: |
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include/dt-bindings/clock/imx8-lpcg.h |
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properties: |
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compatible: |
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oneOf: |
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- const: fsl,imx8qxp-lpcg |
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- items: |
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- enum: |
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- fsl,imx8qm-lpcg |
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- const: fsl,imx8qxp-lpcg |
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- enum: |
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- fsl,imx8qxp-lpcg-adma |
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- fsl,imx8qxp-lpcg-conn |
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- fsl,imx8qxp-lpcg-dc |
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- fsl,imx8qxp-lpcg-dsp |
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- fsl,imx8qxp-lpcg-gpu |
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- fsl,imx8qxp-lpcg-hsio |
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- fsl,imx8qxp-lpcg-img |
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- fsl,imx8qxp-lpcg-lsio |
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- fsl,imx8qxp-lpcg-vpu |
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deprecated: true |
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reg: |
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maxItems: 1 |
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'#clock-cells': |
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const: 1 |
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clocks: |
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description: | |
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Input parent clocks phandle array for each clock |
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minItems: 1 |
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maxItems: 8 |
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clock-indices: |
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description: | |
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An integer array indicating the bit offset for each clock. |
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Refer to <include/dt-bindings/clock/imx8-lpcg.h> for the |
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supported LPCG clock indices. |
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minItems: 1 |
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maxItems: 8 |
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clock-output-names: |
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description: | |
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Shall be the corresponding names of the outputs. |
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NOTE this property must be specified in the same order |
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as the clock-indices property. |
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minItems: 1 |
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maxItems: 8 |
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power-domains: |
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maxItems: 1 |
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required: |
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- compatible |
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- reg |
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- '#clock-cells' |
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additionalProperties: false |
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examples: |
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- | |
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#include <dt-bindings/clock/imx8-lpcg.h> |
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#include <dt-bindings/firmware/imx/rsrc.h> |
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#include <dt-bindings/interrupt-controller/arm-gic.h> |
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sdhc0_lpcg: clock-controller@5b200000 { |
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compatible = "fsl,imx8qxp-lpcg"; |
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reg = <0x5b200000 0x10000>; |
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#clock-cells = <1>; |
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clocks = <&sdhc0_clk IMX_SC_PM_CLK_PER>, |
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<&conn_ipg_clk>, |
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<&conn_axi_clk>; |
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clock-indices = <IMX_LPCG_CLK_0>, |
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<IMX_LPCG_CLK_4>, |
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<IMX_LPCG_CLK_5>; |
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clock-output-names = "sdhc0_lpcg_per_clk", |
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"sdhc0_lpcg_ipg_clk", |
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"sdhc0_lpcg_ahb_clk"; |
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power-domains = <&pd IMX_SC_R_SDHC_0>; |
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}; |
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mmc@5b010000 { |
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compatible = "fsl,imx8qxp-usdhc", "fsl,imx7d-usdhc"; |
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interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>; |
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reg = <0x5b010000 0x10000>; |
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clocks = <&sdhc0_lpcg IMX_LPCG_CLK_4>, |
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<&sdhc0_lpcg IMX_LPCG_CLK_0>, |
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<&sdhc0_lpcg IMX_LPCG_CLK_5>; |
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clock-names = "ipg", "per", "ahb"; |
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power-domains = <&pd IMX_SC_R_SDHC_0>; |
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};
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