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28 lines
842 B
28 lines
842 B
PLL divider based Dove clocks |
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Marvell Dove has a 2GHz PLL, which feeds into a set of dividers to provide |
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high speed clocks for a number of peripherals. These dividers are part of |
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the PMU, and thus this node should be a child of the PMU node. |
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The following clocks are provided: |
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ID Clock |
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0 AXI bus clock |
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1 GPU clock |
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2 VMeta clock |
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3 LCD clock |
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Required properties: |
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- compatible : shall be "marvell,dove-divider-clock" |
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- reg : shall be the register address of the Core PLL and Clock Divider |
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Control 0 register. This will cover that register, as well as the |
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Core PLL and Clock Divider Control 1 register. Thus, it will have |
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a size of 8. |
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- #clock-cells : from common clock binding; shall be set to 1 |
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divider_clk: core-clock@64 { |
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compatible = "marvell,dove-divider-clock"; |
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reg = <0x0064 0x8>; |
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#clock-cells = <1>; |
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};
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