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192 lines
6.1 KiB
192 lines
6.1 KiB
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) |
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# Copyright (C) 2020 BAIKAL ELECTRONICS, JSC |
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%YAML 1.2 |
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--- |
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$id: http://devicetree.org/schemas/clock/baikal,bt1-ccu-div.yaml# |
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$schema: http://devicetree.org/meta-schemas/core.yaml# |
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title: Baikal-T1 Clock Control Unit Dividers |
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maintainers: |
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- Serge Semin <[email protected]> |
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description: | |
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Clocks Control Unit is the core of Baikal-T1 SoC System Controller |
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responsible for the chip subsystems clocking and resetting. The CCU is |
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connected with an external fixed rate oscillator, which signal is transformed |
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into clocks of various frequencies and then propagated to either individual |
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IP-blocks or to groups of blocks (clock domains). The transformation is done |
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by means of an embedded into CCU PLLs and gateable/non-gateable dividers. The |
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later ones are described in this binding. Each clock domain can be also |
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individually reset by using the domain clocks divider configuration |
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registers. Baikal-T1 CCU is logically divided into the next components: |
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1) External oscillator (normally XTAL's 25 MHz crystal oscillator, but |
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in general can provide any frequency supported by the CCU PLLs). |
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2) PLLs clocks generators (PLLs). |
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3) AXI-bus clock dividers (AXI) - described in this binding file. |
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4) System devices reference clock dividers (SYS) - described in this binding |
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file. |
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which are connected with each other as shown on the next figure: |
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+---------------+ |
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| Baikal-T1 CCU | |
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| +----+------|- MIPS P5600 cores |
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| +-|PLLs|------|- DDR controller |
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| | +----+ | |
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+----+ | | | | | |
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|XTAL|--|-+ | | +---+-| |
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+----+ | | | +-|AXI|-|- AXI-bus |
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| | | +---+-| |
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| | | | |
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| | +----+---+-|- APB-bus |
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| +-------|SYS|-|- Low-speed Devices |
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| +---+-|- High-speed Devices |
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+---------------+ |
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Each sub-block is represented as a separate DT node and has an individual |
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driver to be bound with. |
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In order to create signals of wide range frequencies the external oscillator |
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output is primarily connected to a set of CCU PLLs. Some of PLLs CLKOUT are |
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then passed over CCU dividers to create signals required for the target clock |
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domain (like AXI-bus or System Device consumers). The dividers have the |
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following structure: |
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+--------------+ |
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CLKIN --|->+----+ 1|\ | |
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SETCLK--|--|/DIV|->| | | |
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CLKDIV--|--| | | |-|->CLKLOUT |
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LOCK----|--+----+ | | | |
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| |/ | |
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| | | |
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EN------|-----------+ | |
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RST-----|--------------|->RSTOUT |
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+--------------+ |
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where CLKIN is the reference clock coming either from CCU PLLs or from an |
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external clock oscillator, SETCLK - a command to update the output clock in |
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accordance with a set divider, CLKDIV - clocks divider, LOCK - a signal of |
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the output clock stabilization, EN - enable/disable the divider block, |
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RST/RSTOUT - reset clocks domain signal. Depending on the consumer IP-core |
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peculiarities the dividers may lack of some functionality depicted on the |
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figure above (like EN, CLKDIV/LOCK/SETCLK). In this case the corresponding |
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clock provider just doesn't expose either switching functions, or the rate |
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configuration, or both of them. |
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The clock dividers, which output clock is then consumed by the SoC individual |
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devices, are united into a single clocks provider called System Devices CCU. |
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Similarly the dividers with output clocks utilized as AXI-bus reference clocks |
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are called AXI-bus CCU. Both of them use the common clock bindings with no |
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custom properties. The list of exported clocks and reset signals can be found |
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in the files: 'include/dt-bindings/clock/bt1-ccu.h' and |
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'include/dt-bindings/reset/bt1-ccu.h'. Since System Devices and AXI-bus CCU |
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are a part of the Baikal-T1 SoC System Controller their DT nodes are supposed |
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to be a children of later one. |
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if: |
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properties: |
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compatible: |
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contains: |
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const: baikal,bt1-ccu-axi |
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then: |
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properties: |
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clocks: |
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items: |
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- description: CCU SATA PLL output clock |
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- description: CCU PCIe PLL output clock |
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- description: CCU Ethernet PLL output clock |
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clock-names: |
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items: |
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- const: sata_clk |
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- const: pcie_clk |
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- const: eth_clk |
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else: |
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properties: |
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clocks: |
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items: |
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- description: External reference clock |
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- description: CCU SATA PLL output clock |
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- description: CCU PCIe PLL output clock |
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- description: CCU Ethernet PLL output clock |
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clock-names: |
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items: |
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- const: ref_clk |
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- const: sata_clk |
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- const: pcie_clk |
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- const: eth_clk |
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properties: |
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compatible: |
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enum: |
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- baikal,bt1-ccu-axi |
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- baikal,bt1-ccu-sys |
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reg: |
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maxItems: 1 |
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"#clock-cells": |
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const: 1 |
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"#reset-cells": |
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const: 1 |
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clocks: true |
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clock-names: true |
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additionalProperties: false |
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required: |
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- compatible |
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- "#clock-cells" |
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- clocks |
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- clock-names |
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examples: |
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# AXI-bus Clock Control Unit node: |
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- | |
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#include <dt-bindings/clock/bt1-ccu.h> |
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clock-controller@1f04d030 { |
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compatible = "baikal,bt1-ccu-axi"; |
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reg = <0x1f04d030 0x030>; |
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#clock-cells = <1>; |
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#reset-cells = <1>; |
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clocks = <&ccu_pll CCU_SATA_PLL>, |
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<&ccu_pll CCU_PCIE_PLL>, |
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<&ccu_pll CCU_ETH_PLL>; |
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clock-names = "sata_clk", "pcie_clk", "eth_clk"; |
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}; |
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# System Devices Clock Control Unit node: |
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- | |
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#include <dt-bindings/clock/bt1-ccu.h> |
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clock-controller@1f04d060 { |
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compatible = "baikal,bt1-ccu-sys"; |
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reg = <0x1f04d060 0x0a0>; |
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#clock-cells = <1>; |
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#reset-cells = <1>; |
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clocks = <&clk25m>, |
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<&ccu_pll CCU_SATA_PLL>, |
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<&ccu_pll CCU_PCIE_PLL>, |
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<&ccu_pll CCU_ETH_PLL>; |
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clock-names = "ref_clk", "sata_clk", "pcie_clk", |
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"eth_clk"; |
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}; |
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# Required Clock Control Unit PLL node: |
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- | |
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ccu_pll: clock-controller@1f04d000 { |
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compatible = "baikal,bt1-ccu-pll"; |
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reg = <0x1f04d000 0x028>; |
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#clock-cells = <1>; |
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clocks = <&clk25m>; |
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clock-names = "ref_clk"; |
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}; |
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...
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