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77 lines
1.5 KiB
77 lines
1.5 KiB
# SPDX-License-Identifier: GPL-2.0 |
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%YAML 1.2 |
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--- |
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$id: http://devicetree.org/schemas/clock/allwinner,sun4i-a10-tcon-ch0-clk.yaml# |
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$schema: http://devicetree.org/meta-schemas/core.yaml# |
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title: Allwinner A10 TCON Channel 0 Clock Device Tree Bindings |
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maintainers: |
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- Chen-Yu Tsai <[email protected]> |
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- Maxime Ripard <[email protected]> |
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deprecated: true |
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properties: |
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"#clock-cells": |
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const: 0 |
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"#reset-cells": |
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const: 1 |
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compatible: |
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enum: |
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- allwinner,sun4i-a10-tcon-ch0-clk |
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- allwinner,sun4i-a10-tcon-ch1-clk |
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reg: |
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maxItems: 1 |
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clocks: |
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maxItems: 4 |
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description: > |
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The parent order must match the hardware programming order. |
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clock-output-names: |
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maxItems: 1 |
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required: |
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- "#clock-cells" |
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- compatible |
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- reg |
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- clocks |
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- clock-output-names |
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if: |
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properties: |
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compatible: |
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contains: |
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const: allwinner,sun4i-a10-tcon-ch0-clk |
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then: |
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required: |
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- "#reset-cells" |
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additionalProperties: false |
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examples: |
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- | |
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clk@1c20118 { |
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#clock-cells = <0>; |
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#reset-cells = <1>; |
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compatible = "allwinner,sun4i-a10-tcon-ch0-clk"; |
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reg = <0x01c20118 0x4>; |
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clocks = <&pll3>, <&pll7>, <&pll3x2>, <&pll7x2>; |
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clock-output-names = "tcon-ch0-sclk"; |
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}; |
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- | |
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clk@1c2012c { |
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#clock-cells = <0>; |
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compatible = "allwinner,sun4i-a10-tcon-ch1-clk"; |
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reg = <0x01c2012c 0x4>; |
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clocks = <&pll3>, <&pll7>, <&pll3x2>, <&pll7x2>; |
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clock-output-names = "tcon-ch1-sclk"; |
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}; |
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...
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