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72 lines
1.9 KiB
72 lines
1.9 KiB
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) |
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%YAML 1.2 |
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--- |
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$id: "http://devicetree.org/schemas/arm/stm32/st,mlahb.yaml#" |
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$schema: "http://devicetree.org/meta-schemas/core.yaml#" |
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title: STMicroelectronics STM32 ML-AHB interconnect bindings |
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maintainers: |
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- Fabien Dessenne <[email protected]> |
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- Arnaud Pouliquen <[email protected]> |
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description: | |
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These bindings describe the STM32 SoCs ML-AHB interconnect bus which connects |
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a Cortex-M subsystem with dedicated memories. The MCU SRAM and RETRAM memory |
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parts can be accessed through different addresses (see "RAM aliases" in [1]) |
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using different buses (see [2]): balancing the Cortex-M firmware accesses |
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among those ports allows to tune the system performance. |
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[1]: https://www.st.com/resource/en/reference_manual/dm00327659.pdf |
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[2]: https://wiki.st.com/stm32mpu/wiki/STM32MP15_RAM_mapping |
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allOf: |
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- $ref: /schemas/simple-bus.yaml# |
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properties: |
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compatible: |
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contains: |
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enum: |
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- st,mlahb |
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dma-ranges: |
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description: | |
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Describe memory addresses translation between the local CPU and the |
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remote Cortex-M processor. Each memory region, is declared with |
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3 parameters: |
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- param 1: device base address (Cortex-M processor address) |
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- param 2: physical base address (local CPU address) |
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- param 3: size of the memory region. |
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maxItems: 3 |
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'#address-cells': |
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const: 1 |
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'#size-cells': |
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const: 1 |
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required: |
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- compatible |
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- '#address-cells' |
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- '#size-cells' |
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- dma-ranges |
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unevaluatedProperties: false |
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examples: |
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- | |
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mlahb: ahb@38000000 { |
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compatible = "st,mlahb", "simple-bus"; |
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#address-cells = <1>; |
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#size-cells = <1>; |
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reg = <0x10000000 0x40000>; |
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ranges; |
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dma-ranges = <0x00000000 0x38000000 0x10000>, |
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<0x10000000 0x10000000 0x60000>, |
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<0x30000000 0x30000000 0x60000>; |
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m4_rproc: m4@10000000 { |
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reg = <0x10000000 0x40000>; |
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}; |
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}; |
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...
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