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102 lines
2.6 KiB
102 lines
2.6 KiB
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause |
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%YAML 1.2 |
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--- |
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$id: http://devicetree.org/schemas/arm/socionext/socionext,uniphier-system-cache.yaml# |
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$schema: http://devicetree.org/meta-schemas/core.yaml# |
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title: UniPhier outer cache controller |
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description: | |
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UniPhier ARM 32-bit SoCs are integrated with a full-custom outer cache |
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controller system. All of them have a level 2 cache controller, and some |
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have a level 3 cache controller as well. |
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maintainers: |
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- Masahiro Yamada <[email protected]> |
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properties: |
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compatible: |
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const: socionext,uniphier-system-cache |
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reg: |
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description: | |
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should contain 3 regions: control register, revision register, |
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operation register, in this order. |
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minItems: 3 |
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maxItems: 3 |
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interrupts: |
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description: | |
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Interrupts can be used to notify the completion of cache operations. |
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The number of interrupts should match to the number of CPU cores. |
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The specified interrupts correspond to CPU0, CPU1, ... in this order. |
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minItems: 1 |
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maxItems: 4 |
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cache-unified: true |
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cache-size: true |
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cache-sets: true |
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cache-line-size: true |
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cache-level: |
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minimum: 2 |
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maximum: 3 |
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next-level-cache: true |
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allOf: |
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- $ref: /schemas/cache-controller.yaml# |
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additionalProperties: false |
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required: |
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- compatible |
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- reg |
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- interrupts |
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- cache-unified |
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- cache-size |
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- cache-sets |
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- cache-line-size |
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- cache-level |
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examples: |
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- | |
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// System with L2. |
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cache-controller@500c0000 { |
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compatible = "socionext,uniphier-system-cache"; |
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reg = <0x500c0000 0x2000>, <0x503c0100 0x4>, <0x506c0000 0x400>; |
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interrupts = <0 174 4>, <0 175 4>, <0 190 4>, <0 191 4>; |
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cache-unified; |
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cache-size = <0x140000>; |
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cache-sets = <512>; |
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cache-line-size = <128>; |
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cache-level = <2>; |
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}; |
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- | |
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// System with L2 and L3. |
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// L2 should specify the next level cache by 'next-level-cache'. |
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l2: cache-controller@500c0000 { |
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compatible = "socionext,uniphier-system-cache"; |
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reg = <0x500c0000 0x2000>, <0x503c0100 0x8>, <0x506c0000 0x400>; |
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interrupts = <0 190 4>, <0 191 4>; |
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cache-unified; |
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cache-size = <0x200000>; |
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cache-sets = <512>; |
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cache-line-size = <128>; |
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cache-level = <2>; |
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next-level-cache = <&l3>; |
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}; |
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l3: cache-controller@500c8000 { |
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compatible = "socionext,uniphier-system-cache"; |
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reg = <0x500c8000 0x2000>, <0x503c8100 0x8>, <0x506c8000 0x400>; |
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interrupts = <0 174 4>, <0 175 4>; |
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cache-unified; |
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cache-size = <0x200000>; |
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cache-sets = <512>; |
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cache-line-size = <256>; |
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cache-level = <3>; |
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};
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