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397 lines
10 KiB
397 lines
10 KiB
* CoreSight Components: |
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CoreSight components are compliant with the ARM CoreSight architecture |
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specification and can be connected in various topologies to suit a particular |
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SoCs tracing needs. These trace components can generally be classified as |
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sinks, links and sources. Trace data produced by one or more sources flows |
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through the intermediate links connecting the source to the currently selected |
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sink. Each CoreSight component device should use these properties to describe |
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its hardware characteristcs. |
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* Required properties for all components *except* non-configurable replicators |
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and non-configurable funnels: |
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* compatible: These have to be supplemented with "arm,primecell" as |
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drivers are using the AMBA bus interface. Possible values include: |
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- Embedded Trace Buffer (version 1.0): |
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"arm,coresight-etb10", "arm,primecell"; |
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- Trace Port Interface Unit: |
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"arm,coresight-tpiu", "arm,primecell"; |
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- Trace Memory Controller, used for Embedded Trace Buffer(ETB), |
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Embedded Trace FIFO(ETF) and Embedded Trace Router(ETR) |
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configuration. The configuration mode (ETB, ETF, ETR) is |
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discovered at boot time when the device is probed. |
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"arm,coresight-tmc", "arm,primecell"; |
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- Trace Programmable Funnel: |
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"arm,coresight-dynamic-funnel", "arm,primecell"; |
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"arm,coresight-funnel", "arm,primecell"; (OBSOLETE. For |
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backward compatibility and will be removed) |
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- Embedded Trace Macrocell (version 3.x) and |
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Program Flow Trace Macrocell: |
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"arm,coresight-etm3x", "arm,primecell"; |
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- Embedded Trace Macrocell (version 4.x), with memory mapped access. |
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"arm,coresight-etm4x", "arm,primecell"; |
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- Embedded Trace Macrocell (version 4.x), with system register access only. |
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"arm,coresight-etm4x-sysreg"; |
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- Coresight programmable Replicator : |
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"arm,coresight-dynamic-replicator", "arm,primecell"; |
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- System Trace Macrocell: |
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"arm,coresight-stm", "arm,primecell"; [1] |
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- Coresight Address Translation Unit (CATU) |
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"arm,coresight-catu", "arm,primecell"; |
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- Coresight Cross Trigger Interface (CTI): |
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"arm,coresight-cti", "arm,primecell"; |
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See coresight-cti.yaml for full CTI definitions. |
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* reg: physical base address and length of the register |
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set(s) of the component. |
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* clocks: the clocks associated to this component. |
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* clock-names: the name of the clocks referenced by the code. |
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Since we are using the AMBA framework, the name of the clock |
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providing the interconnect should be "apb_pclk", and some |
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coresight blocks also have an additional clock "atclk", which |
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clocks the core of that coresight component. The latter clock |
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is optional. |
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* port or ports: see "Graph bindings for Coresight" below. |
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* Additional required property for Embedded Trace Macrocell (version 3.x and |
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version 4.x): |
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* cpu: the cpu phandle this ETM/PTM is affined to. Do not |
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assume it to default to CPU0 if omitted. |
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* Additional required properties for System Trace Macrocells (STM): |
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* reg: along with the physical base address and length of the register |
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set as described above, another entry is required to describe the |
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mapping of the extended stimulus port area. |
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* reg-names: the only acceptable values are "stm-base" and |
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"stm-stimulus-base", each corresponding to the areas defined in "reg". |
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* Required properties for Coresight Cross Trigger Interface (CTI) |
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See coresight-cti.yaml for full CTI definitions. |
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* Required properties for devices that don't show up on the AMBA bus, such as |
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non-configurable replicators and non-configurable funnels: |
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* compatible: Currently supported value is (note the absence of the |
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AMBA markee): |
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- Coresight Non-configurable Replicator: |
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"arm,coresight-static-replicator"; |
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"arm,coresight-replicator"; (OBSOLETE. For backward |
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compatibility and will be removed) |
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- Coresight Non-configurable Funnel: |
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"arm,coresight-static-funnel"; |
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* port or ports: see "Graph bindings for Coresight" below. |
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* Optional properties for all components: |
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* arm,coresight-loses-context-with-cpu : boolean. Indicates that the |
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hardware will lose register context on CPU power down (e.g. CPUIdle). |
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An example of where this may be needed are systems which contain a |
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coresight component and CPU in the same power domain. When the CPU |
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powers down the coresight component also powers down and loses its |
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context. This property is currently only used for the ETM 4.x driver. |
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* Optional properties for ETM/PTMs: |
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* arm,cp14: must be present if the system accesses ETM/PTM management |
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registers via co-processor 14. |
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* qcom,skip-power-up: boolean. Indicates that an implementation can |
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skip powering up the trace unit. TRCPDCR.PU does not have to be set |
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on Qualcomm Technologies Inc. systems since ETMs are in the same power |
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domain as their CPU cores. This property is required to identify such |
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systems with hardware errata where the CPU watchdog counter is stopped |
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when TRCPDCR.PU is set. |
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* Optional property for TMC: |
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* arm,buffer-size: size of contiguous buffer space for TMC ETR |
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(embedded trace router). This property is obsolete. The buffer size |
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can be configured dynamically via buffer_size property in sysfs. |
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* arm,scatter-gather: boolean. Indicates that the TMC-ETR can safely |
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use the SG mode on this system. |
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* Optional property for CATU : |
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* interrupts : Exactly one SPI may be listed for reporting the address |
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error |
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* Optional property for configurable replicators: |
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* qcom,replicator-loses-context: boolean. Indicates that the replicator |
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will lose register context when AMBA clock is removed which is observed |
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in some replicator designs. |
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Graph bindings for Coresight |
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------------------------------- |
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Coresight components are interconnected to create a data path for the flow of |
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trace data generated from the "sources" to their collection points "sink". |
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Each coresight component must describe the "input" and "output" connections. |
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The connections must be described via generic DT graph bindings as described |
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by the "bindings/graph.txt", where each "port" along with an "endpoint" |
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component represents a hardware port and the connection. |
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* All output ports must be listed inside a child node named "out-ports" |
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* All input ports must be listed inside a child node named "in-ports". |
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* Port address must match the hardware port number. |
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Example: |
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1. Sinks |
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etb@20010000 { |
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compatible = "arm,coresight-etb10", "arm,primecell"; |
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reg = <0 0x20010000 0 0x1000>; |
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clocks = <&oscclk6a>; |
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clock-names = "apb_pclk"; |
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in-ports { |
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port { |
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etb_in_port: endpoint@0 { |
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remote-endpoint = <&replicator_out_port0>; |
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}; |
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}; |
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}; |
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}; |
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tpiu@20030000 { |
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compatible = "arm,coresight-tpiu", "arm,primecell"; |
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reg = <0 0x20030000 0 0x1000>; |
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clocks = <&oscclk6a>; |
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clock-names = "apb_pclk"; |
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in-ports { |
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port { |
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tpiu_in_port: endpoint@0 { |
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remote-endpoint = <&replicator_out_port1>; |
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}; |
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}; |
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}; |
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}; |
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etr@20070000 { |
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compatible = "arm,coresight-tmc", "arm,primecell"; |
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reg = <0 0x20070000 0 0x1000>; |
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clocks = <&oscclk6a>; |
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clock-names = "apb_pclk"; |
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in-ports { |
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port { |
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etr_in_port: endpoint { |
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remote-endpoint = <&replicator2_out_port0>; |
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}; |
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}; |
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}; |
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out-ports { |
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port { |
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etr_out_port: endpoint { |
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remote-endpoint = <&catu_in_port>; |
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}; |
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}; |
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}; |
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}; |
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2. Links |
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replicator { |
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/* non-configurable replicators don't show up on the |
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* AMBA bus. As such no need to add "arm,primecell". |
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*/ |
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compatible = "arm,coresight-static-replicator"; |
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out-ports { |
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#address-cells = <1>; |
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#size-cells = <0>; |
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/* replicator output ports */ |
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port@0 { |
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reg = <0>; |
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replicator_out_port0: endpoint { |
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remote-endpoint = <&etb_in_port>; |
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}; |
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}; |
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port@1 { |
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reg = <1>; |
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replicator_out_port1: endpoint { |
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remote-endpoint = <&tpiu_in_port>; |
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}; |
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}; |
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}; |
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in-ports { |
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port { |
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replicator_in_port0: endpoint { |
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remote-endpoint = <&funnel_out_port0>; |
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}; |
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}; |
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}; |
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}; |
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funnel { |
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/* |
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* non-configurable funnel don't show up on the AMBA |
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* bus. As such no need to add "arm,primecell". |
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*/ |
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compatible = "arm,coresight-static-funnel"; |
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clocks = <&crg_ctrl HI3660_PCLK>; |
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clock-names = "apb_pclk"; |
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out-ports { |
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port { |
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combo_funnel_out: endpoint { |
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remote-endpoint = <&top_funnel_in>; |
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}; |
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}; |
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}; |
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in-ports { |
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#address-cells = <1>; |
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#size-cells = <0>; |
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port@0 { |
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reg = <0>; |
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combo_funnel_in0: endpoint { |
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remote-endpoint = <&cluster0_etf_out>; |
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}; |
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}; |
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port@1 { |
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reg = <1>; |
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combo_funnel_in1: endpoint { |
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remote-endpoint = <&cluster1_etf_out>; |
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}; |
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}; |
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}; |
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}; |
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funnel@20040000 { |
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compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; |
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reg = <0 0x20040000 0 0x1000>; |
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clocks = <&oscclk6a>; |
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clock-names = "apb_pclk"; |
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out-ports { |
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port { |
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funnel_out_port0: endpoint { |
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remote-endpoint = |
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<&replicator_in_port0>; |
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}; |
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}; |
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}; |
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in-ports { |
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#address-cells = <1>; |
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#size-cells = <0>; |
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port@0 { |
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reg = <0>; |
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funnel_in_port0: endpoint { |
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remote-endpoint = <&ptm0_out_port>; |
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}; |
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}; |
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port@1 { |
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reg = <1>; |
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funnel_in_port1: endpoint { |
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remote-endpoint = <&ptm1_out_port>; |
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}; |
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}; |
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port@2 { |
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reg = <2>; |
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funnel_in_port2: endpoint { |
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remote-endpoint = <&etm0_out_port>; |
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}; |
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}; |
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}; |
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}; |
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3. Sources |
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ptm@2201c000 { |
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compatible = "arm,coresight-etm3x", "arm,primecell"; |
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reg = <0 0x2201c000 0 0x1000>; |
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cpu = <&cpu0>; |
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clocks = <&oscclk6a>; |
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clock-names = "apb_pclk"; |
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out-ports { |
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port { |
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ptm0_out_port: endpoint { |
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remote-endpoint = <&funnel_in_port0>; |
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}; |
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}; |
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}; |
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}; |
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ptm@2201d000 { |
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compatible = "arm,coresight-etm3x", "arm,primecell"; |
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reg = <0 0x2201d000 0 0x1000>; |
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cpu = <&cpu1>; |
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clocks = <&oscclk6a>; |
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clock-names = "apb_pclk"; |
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out-ports { |
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port { |
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ptm1_out_port: endpoint { |
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remote-endpoint = <&funnel_in_port1>; |
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}; |
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}; |
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}; |
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}; |
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4. STM |
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stm@20100000 { |
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compatible = "arm,coresight-stm", "arm,primecell"; |
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reg = <0 0x20100000 0 0x1000>, |
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<0 0x28000000 0 0x180000>; |
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reg-names = "stm-base", "stm-stimulus-base"; |
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clocks = <&soc_smc50mhz>; |
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clock-names = "apb_pclk"; |
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out-ports { |
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port { |
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stm_out_port: endpoint { |
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remote-endpoint = <&main_funnel_in_port2>; |
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}; |
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}; |
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}; |
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}; |
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5. CATU |
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catu@207e0000 { |
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compatible = "arm,coresight-catu", "arm,primecell"; |
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reg = <0 0x207e0000 0 0x1000>; |
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clocks = <&oscclk6a>; |
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clock-names = "apb_pclk"; |
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interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; |
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in-ports { |
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port { |
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catu_in_port: endpoint { |
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remote-endpoint = <&etr_out_port>; |
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}; |
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}; |
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}; |
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}; |
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[1]. There is currently two version of STM: STM32 and STM500. Both |
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have the same HW interface and as such don't need an explicit binding name.
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