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265 lines
7.2 KiB
265 lines
7.2 KiB
ARM Broadcom STB platforms Device Tree Bindings |
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----------------------------------------------- |
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Boards with Broadcom Brahma15 ARM-based BCMxxxx (generally BCM7xxx variants) |
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SoC shall have the following DT organization: |
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Required root node properties: |
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- compatible: "brcm,bcm<chip_id>", "brcm,brcmstb" |
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example: |
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/ { |
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#address-cells = <2>; |
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#size-cells = <2>; |
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model = "Broadcom STB (bcm7445)"; |
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compatible = "brcm,bcm7445", "brcm,brcmstb"; |
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Further, syscon nodes that map platform-specific registers used for general |
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system control is required: |
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- compatible: "brcm,bcm<chip_id>-sun-top-ctrl", "syscon" |
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- compatible: "brcm,bcm<chip_id>-cpu-biu-ctrl", |
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"brcm,brcmstb-cpu-biu-ctrl", |
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"syscon" |
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- compatible: "brcm,bcm<chip_id>-hif-continuation", "syscon" |
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cpu-biu-ctrl node |
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------------------- |
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SoCs with Broadcom Brahma15 ARM-based and Brahma53 ARM64-based CPUs have a |
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specific Bus Interface Unit (BIU) block which controls and interfaces the CPU |
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complex to the different Memory Controller Ports (MCP), one per memory |
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controller (MEMC). This BIU block offers a feature called Write Pairing which |
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consists in collapsing two adjacent cache lines into a single (bursted) write |
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transaction towards the memory controller (MEMC) to maximize write bandwidth. |
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Required properties: |
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- compatible: must be "brcm,bcm7445-cpu-biu-ctrl", "brcm,brcmstb-cpu-biu-ctrl", "syscon" |
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Optional properties: |
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- brcm,write-pairing: |
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Boolean property, which when present indicates that the chip |
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supports write-pairing. |
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example: |
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rdb { |
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#address-cells = <1>; |
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#size-cells = <1>; |
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compatible = "simple-bus"; |
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ranges = <0 0x00 0xf0000000 0x1000000>; |
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sun_top_ctrl: syscon@404000 { |
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compatible = "brcm,bcm7445-sun-top-ctrl", "syscon"; |
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reg = <0x404000 0x51c>; |
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}; |
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hif_cpubiuctrl: syscon@3e2400 { |
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compatible = "brcm,bcm7445-cpu-biu-ctrl", "brcm,brcmstb-cpu-biu-ctrl", "syscon"; |
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reg = <0x3e2400 0x5b4>; |
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brcm,write-pairing; |
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}; |
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hif_continuation: syscon@452000 { |
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compatible = "brcm,bcm7445-hif-continuation", "syscon"; |
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reg = <0x452000 0x100>; |
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}; |
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}; |
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Nodes that allow for support of SMP initialization and reboot are required: |
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smpboot |
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------- |
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Required properties: |
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- compatible |
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The string "brcm,brcmstb-smpboot". |
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- syscon-cpu |
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A phandle / integer array property which lets the BSP know the location |
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of certain CPU power-on registers. |
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The layout of the property is as follows: |
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o a phandle to the "hif_cpubiuctrl" syscon node |
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o offset to the base CPU power zone register |
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o offset to the base CPU reset register |
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- syscon-cont |
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A phandle pointing to the syscon node which describes the CPU boot |
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continuation registers. |
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o a phandle to the "hif_continuation" syscon node |
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example: |
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smpboot { |
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compatible = "brcm,brcmstb-smpboot"; |
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syscon-cpu = <&hif_cpubiuctrl 0x88 0x178>; |
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syscon-cont = <&hif_continuation>; |
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}; |
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reboot |
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------- |
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Required properties |
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- compatible |
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The string property "brcm,brcmstb-reboot" for 40nm/28nm chips with |
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the new SYS_CTRL interface, or "brcm,bcm7038-reboot" for 65nm |
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chips with the old SUN_TOP_CTRL interface. |
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- syscon |
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A phandle / integer array that points to the syscon node which describes |
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the general system reset registers. |
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o a phandle to "sun_top_ctrl" |
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o offset to the "reset source enable" register |
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o offset to the "software master reset" register |
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example: |
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reboot { |
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compatible = "brcm,brcmstb-reboot"; |
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syscon = <&sun_top_ctrl 0x304 0x308>; |
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}; |
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Power management |
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---------------- |
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For power management (particularly, S2/S3/S5 system suspend), the following SoC |
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components are needed: |
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= Always-On control block (AON CTRL) |
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This hardware provides control registers for the "always-on" (even in low-power |
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modes) hardware, such as the Power Management State Machine (PMSM). |
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Required properties: |
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- compatible : should contain "brcm,brcmstb-aon-ctrl" |
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- reg : the register start and length for the AON CTRL block |
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Example: |
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aon-ctrl@410000 { |
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compatible = "brcm,brcmstb-aon-ctrl"; |
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reg = <0x410000 0x400>; |
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}; |
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= Memory controllers |
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A Broadcom STB SoC typically has a number of independent memory controllers, |
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each of which may have several associated hardware blocks, which are versioned |
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independently (control registers, DDR PHYs, etc.). One might consider |
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describing these controllers as a parent "memory controllers" block, which |
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contains N sub-nodes (one for each controller in the system), each of which is |
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associated with a number of hardware register resources (e.g., its PHY). See |
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the example device tree snippet below. |
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== MEMC (MEMory Controller) |
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Represents a single memory controller instance. |
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Required properties: |
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- compatible : should contain "brcm,brcmstb-memc" and "simple-bus" |
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Should contain subnodes for any of the following relevant hardware resources: |
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== DDR PHY control |
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Control registers for this memory controller's DDR PHY. |
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Required properties: |
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- compatible : should contain one of these |
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"brcm,brcmstb-ddr-phy-v71.1" |
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"brcm,brcmstb-ddr-phy-v72.0" |
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"brcm,brcmstb-ddr-phy-v225.1" |
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"brcm,brcmstb-ddr-phy-v240.1" |
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"brcm,brcmstb-ddr-phy-v240.2" |
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- reg : the DDR PHY register range |
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== DDR SHIMPHY |
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Control registers for this memory controller's DDR SHIMPHY. |
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Required properties: |
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- compatible : should contain "brcm,brcmstb-ddr-shimphy-v1.0" |
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- reg : the DDR SHIMPHY register range |
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== MEMC DDR control |
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Sequencer DRAM parameters and control registers. Used for Self-Refresh |
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Power-Down (SRPD), among other things. |
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Required properties: |
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- compatible : should contain one of these |
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"brcm,brcmstb-memc-ddr-rev-b.2.1" |
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"brcm,brcmstb-memc-ddr-rev-b.2.2" |
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"brcm,brcmstb-memc-ddr-rev-b.2.3" |
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"brcm,brcmstb-memc-ddr-rev-b.3.0" |
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"brcm,brcmstb-memc-ddr-rev-b.3.1" |
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"brcm,brcmstb-memc-ddr" |
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- reg : the MEMC DDR register range |
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Example: |
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memory_controllers { |
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ranges; |
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compatible = "simple-bus"; |
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memc@0 { |
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compatible = "brcm,brcmstb-memc", "simple-bus"; |
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ranges; |
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ddr-phy@f1106000 { |
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compatible = "brcm,brcmstb-ddr-phy-v240.1"; |
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reg = <0xf1106000 0x21c>; |
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}; |
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shimphy@f1108000 { |
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compatible = "brcm,brcmstb-ddr-shimphy-v1.0"; |
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reg = <0xf1108000 0xe4>; |
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}; |
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memc-ddr@f1102000 { |
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reg = <0xf1102000 0x800>; |
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compatible = "brcm,brcmstb-memc-ddr"; |
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}; |
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}; |
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memc@1 { |
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compatible = "brcm,brcmstb-memc", "simple-bus"; |
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ranges; |
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ddr-phy@f1186000 { |
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compatible = "brcm,brcmstb-ddr-phy-v240.1"; |
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reg = <0xf1186000 0x21c>; |
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}; |
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shimphy@f1188000 { |
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compatible = "brcm,brcmstb-ddr-shimphy-v1.0"; |
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reg = <0xf1188000 0xe4>; |
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}; |
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memc-ddr@f1182000 { |
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reg = <0xf1182000 0x800>; |
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compatible = "brcm,brcmstb-memc-ddr"; |
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}; |
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}; |
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memc@2 { |
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compatible = "brcm,brcmstb-memc", "simple-bus"; |
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ranges; |
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ddr-phy@f1206000 { |
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compatible = "brcm,brcmstb-ddr-phy-v240.1"; |
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reg = <0xf1206000 0x21c>; |
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}; |
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shimphy@f1208000 { |
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compatible = "brcm,brcmstb-ddr-shimphy-v1.0"; |
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reg = <0xf1208000 0xe4>; |
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}; |
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memc-ddr@f1202000 { |
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reg = <0xf1202000 0x800>; |
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compatible = "brcm,brcmstb-memc-ddr"; |
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}; |
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}; |
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};
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