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44 lines
1.1 KiB
44 lines
1.1 KiB
/* |
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* Copyright (c) 2013 Samsung Electronics Co., Ltd. |
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* Author: Andrzej Hajda <[email protected]> |
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* |
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* This program is free software; you can redistribute it and/or modify |
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* it under the terms of the GNU General Public License version 2 as |
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* published by the Free Software Foundation. |
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* |
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* Device Tree binding constants for Exynos5440 clock controller. |
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*/ |
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#ifndef _DT_BINDINGS_CLOCK_EXYNOS_5440_H |
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#define _DT_BINDINGS_CLOCK_EXYNOS_5440_H |
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#define CLK_XTAL 1 |
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#define CLK_ARM_CLK 2 |
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#define CLK_CPLLA 3 |
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#define CLK_CPLLB 4 |
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#define CLK_SPI_BAUD 16 |
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#define CLK_PB0_250 17 |
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#define CLK_PR0_250 18 |
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#define CLK_PR1_250 19 |
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#define CLK_B_250 20 |
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#define CLK_B_125 21 |
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#define CLK_B_200 22 |
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#define CLK_SATA 23 |
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#define CLK_USB 24 |
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#define CLK_GMAC0 25 |
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#define CLK_CS250 26 |
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#define CLK_PB0_250_O 27 |
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#define CLK_PR0_250_O 28 |
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#define CLK_PR1_250_O 29 |
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#define CLK_B_250_O 30 |
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#define CLK_B_125_O 31 |
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#define CLK_B_200_O 32 |
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#define CLK_SATA_O 33 |
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#define CLK_USB_O 34 |
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#define CLK_GMAC0_O 35 |
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#define CLK_CS250_O 36 |
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/* must be greater than maximal clock id */ |
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#define CLK_NR_CLKS 37 |
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#endif /* _DT_BINDINGS_CLOCK_EXYNOS_5440_H */
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