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217 lines
5.8 KiB
217 lines
5.8 KiB
// SPDX-License-Identifier: GPL-2.0 |
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/* |
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* Copyright (c) 2020 Yangtao Li <[email protected]> |
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*/ |
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#include <linux/clk-provider.h> |
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#include <linux/module.h> |
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#include <linux/platform_device.h> |
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#include "ccu_common.h" |
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#include "ccu_reset.h" |
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#include "ccu_div.h" |
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#include "ccu_gate.h" |
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#include "ccu_mp.h" |
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#include "ccu_nm.h" |
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#include "ccu-sun50i-a100-r.h" |
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static const char * const cpus_r_apb2_parents[] = { "dcxo24M", "osc32k", |
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"iosc", "pll-periph0" }; |
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static const struct ccu_mux_var_prediv cpus_r_apb2_predivs[] = { |
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{ .index = 3, .shift = 0, .width = 5 }, |
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}; |
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static struct ccu_div r_cpus_clk = { |
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.div = _SUNXI_CCU_DIV_FLAGS(8, 2, CLK_DIVIDER_POWER_OF_TWO), |
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.mux = { |
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.shift = 24, |
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.width = 2, |
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.var_predivs = cpus_r_apb2_predivs, |
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.n_var_predivs = ARRAY_SIZE(cpus_r_apb2_predivs), |
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}, |
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.common = { |
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.reg = 0x000, |
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.features = CCU_FEATURE_VARIABLE_PREDIV, |
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.hw.init = CLK_HW_INIT_PARENTS("cpus", |
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cpus_r_apb2_parents, |
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&ccu_div_ops, |
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0), |
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}, |
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}; |
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static CLK_FIXED_FACTOR_HW(r_ahb_clk, "r-ahb", &r_cpus_clk.common.hw, 1, 1, 0); |
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static struct ccu_div r_apb1_clk = { |
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.div = _SUNXI_CCU_DIV(0, 2), |
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.common = { |
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.reg = 0x00c, |
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.hw.init = CLK_HW_INIT("r-apb1", |
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"r-ahb", |
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&ccu_div_ops, |
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0), |
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}, |
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}; |
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static struct ccu_div r_apb2_clk = { |
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.div = _SUNXI_CCU_DIV_FLAGS(8, 2, CLK_DIVIDER_POWER_OF_TWO), |
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.mux = { |
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.shift = 24, |
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.width = 2, |
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.var_predivs = cpus_r_apb2_predivs, |
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.n_var_predivs = ARRAY_SIZE(cpus_r_apb2_predivs), |
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}, |
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.common = { |
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.reg = 0x010, |
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.features = CCU_FEATURE_VARIABLE_PREDIV, |
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.hw.init = CLK_HW_INIT_PARENTS("r-apb2", |
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cpus_r_apb2_parents, |
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&ccu_div_ops, |
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0), |
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}, |
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}; |
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static const struct clk_parent_data clk_parent_r_apb1[] = { |
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{ .hw = &r_apb1_clk.common.hw }, |
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}; |
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static const struct clk_parent_data clk_parent_r_apb2[] = { |
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{ .hw = &r_apb2_clk.common.hw }, |
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}; |
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static SUNXI_CCU_GATE_DATA(r_apb1_timer_clk, "r-apb1-timer", clk_parent_r_apb1, |
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0x11c, BIT(0), 0); |
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static SUNXI_CCU_GATE_DATA(r_apb1_twd_clk, "r-apb1-twd", clk_parent_r_apb1, |
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0x12c, BIT(0), 0); |
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static const char * const r_apb1_pwm_clk_parents[] = { "dcxo24M", "osc32k", |
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"iosc" }; |
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static SUNXI_CCU_MUX(r_apb1_pwm_clk, "r-apb1-pwm", r_apb1_pwm_clk_parents, |
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0x130, 24, 2, 0); |
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static SUNXI_CCU_GATE_DATA(r_apb1_bus_pwm_clk, "r-apb1-bus-pwm", |
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clk_parent_r_apb1, 0x13c, BIT(0), 0); |
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static SUNXI_CCU_GATE_DATA(r_apb1_ppu_clk, "r-apb1-ppu", clk_parent_r_apb1, |
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0x17c, BIT(0), 0); |
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static SUNXI_CCU_GATE_DATA(r_apb2_uart_clk, "r-apb2-uart", clk_parent_r_apb2, |
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0x18c, BIT(0), 0); |
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static SUNXI_CCU_GATE_DATA(r_apb2_i2c0_clk, "r-apb2-i2c0", clk_parent_r_apb2, |
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0x19c, BIT(0), 0); |
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static SUNXI_CCU_GATE_DATA(r_apb2_i2c1_clk, "r-apb2-i2c1", clk_parent_r_apb2, |
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0x19c, BIT(1), 0); |
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static const char * const r_apb1_ir_rx_parents[] = { "osc32k", "dcxo24M" }; |
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static SUNXI_CCU_MP_WITH_MUX_GATE(r_apb1_ir_rx_clk, "r-apb1-ir-rx", |
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r_apb1_ir_rx_parents, 0x1c0, |
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0, 5, /* M */ |
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8, 2, /* P */ |
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24, 1, /* mux */ |
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BIT(31), /* gate */ |
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0); |
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static SUNXI_CCU_GATE_DATA(r_apb1_bus_ir_rx_clk, "r-apb1-bus-ir-rx", |
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clk_parent_r_apb1, 0x1cc, BIT(0), 0); |
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static SUNXI_CCU_GATE(r_ahb_bus_rtc_clk, "r-ahb-rtc", "r-ahb", |
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0x20c, BIT(0), 0); |
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static struct ccu_common *sun50i_a100_r_ccu_clks[] = { |
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&r_cpus_clk.common, |
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&r_apb1_clk.common, |
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&r_apb2_clk.common, |
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&r_apb1_timer_clk.common, |
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&r_apb1_twd_clk.common, |
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&r_apb1_pwm_clk.common, |
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&r_apb1_bus_pwm_clk.common, |
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&r_apb1_ppu_clk.common, |
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&r_apb2_uart_clk.common, |
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&r_apb2_i2c0_clk.common, |
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&r_apb2_i2c1_clk.common, |
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&r_apb1_ir_rx_clk.common, |
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&r_apb1_bus_ir_rx_clk.common, |
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&r_ahb_bus_rtc_clk.common, |
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}; |
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static struct clk_hw_onecell_data sun50i_a100_r_hw_clks = { |
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.hws = { |
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[CLK_R_CPUS] = &r_cpus_clk.common.hw, |
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[CLK_R_AHB] = &r_ahb_clk.hw, |
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[CLK_R_APB1] = &r_apb1_clk.common.hw, |
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[CLK_R_APB2] = &r_apb2_clk.common.hw, |
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[CLK_R_APB1_TIMER] = &r_apb1_timer_clk.common.hw, |
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[CLK_R_APB1_TWD] = &r_apb1_twd_clk.common.hw, |
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[CLK_R_APB1_PWM] = &r_apb1_pwm_clk.common.hw, |
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[CLK_R_APB1_BUS_PWM] = &r_apb1_bus_pwm_clk.common.hw, |
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[CLK_R_APB1_PPU] = &r_apb1_ppu_clk.common.hw, |
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[CLK_R_APB2_UART] = &r_apb2_uart_clk.common.hw, |
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[CLK_R_APB2_I2C0] = &r_apb2_i2c0_clk.common.hw, |
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[CLK_R_APB2_I2C1] = &r_apb2_i2c1_clk.common.hw, |
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[CLK_R_APB1_IR] = &r_apb1_ir_rx_clk.common.hw, |
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[CLK_R_APB1_BUS_IR] = &r_apb1_bus_ir_rx_clk.common.hw, |
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[CLK_R_AHB_BUS_RTC] = &r_ahb_bus_rtc_clk.common.hw, |
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}, |
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.num = CLK_NUMBER, |
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}; |
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static struct ccu_reset_map sun50i_a100_r_ccu_resets[] = { |
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[RST_R_APB1_TIMER] = { 0x11c, BIT(16) }, |
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[RST_R_APB1_BUS_PWM] = { 0x13c, BIT(16) }, |
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[RST_R_APB1_PPU] = { 0x17c, BIT(16) }, |
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[RST_R_APB2_UART] = { 0x18c, BIT(16) }, |
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[RST_R_APB2_I2C0] = { 0x19c, BIT(16) }, |
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[RST_R_APB2_I2C1] = { 0x19c, BIT(17) }, |
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[RST_R_APB1_BUS_IR] = { 0x1cc, BIT(16) }, |
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[RST_R_AHB_BUS_RTC] = { 0x20c, BIT(16) }, |
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}; |
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static const struct sunxi_ccu_desc sun50i_a100_r_ccu_desc = { |
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.ccu_clks = sun50i_a100_r_ccu_clks, |
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.num_ccu_clks = ARRAY_SIZE(sun50i_a100_r_ccu_clks), |
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.hw_clks = &sun50i_a100_r_hw_clks, |
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.resets = sun50i_a100_r_ccu_resets, |
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.num_resets = ARRAY_SIZE(sun50i_a100_r_ccu_resets), |
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}; |
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static int sun50i_a100_r_ccu_probe(struct platform_device *pdev) |
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{ |
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void __iomem *reg; |
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reg = devm_platform_ioremap_resource(pdev, 0); |
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if (IS_ERR(reg)) |
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return PTR_ERR(reg); |
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return devm_sunxi_ccu_probe(&pdev->dev, reg, &sun50i_a100_r_ccu_desc); |
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} |
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static const struct of_device_id sun50i_a100_r_ccu_ids[] = { |
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{ .compatible = "allwinner,sun50i-a100-r-ccu" }, |
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{ } |
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}; |
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static struct platform_driver sun50i_a100_r_ccu_driver = { |
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.probe = sun50i_a100_r_ccu_probe, |
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.driver = { |
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.name = "sun50i-a100-r-ccu", |
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.suppress_bind_attrs = true, |
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.of_match_table = sun50i_a100_r_ccu_ids, |
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}, |
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}; |
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module_platform_driver(sun50i_a100_r_ccu_driver); |
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MODULE_IMPORT_NS(SUNXI_CCU); |
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MODULE_LICENSE("GPL");
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