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74 lines
1.9 KiB
74 lines
1.9 KiB
// SPDX-License-Identifier: GPL-2.0-only |
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/* |
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* Copyright (c) 2014 MediaTek Inc. |
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* Author: Shunli Wang <[email protected]> |
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*/ |
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#include <linux/clk-provider.h> |
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#include <linux/platform_device.h> |
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#include "clk-mtk.h" |
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#include "clk-gate.h" |
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#include <dt-bindings/clock/mt2701-clk.h> |
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static const struct mtk_gate_regs eth_cg_regs = { |
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.sta_ofs = 0x0030, |
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}; |
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#define GATE_ETH(_id, _name, _parent, _shift) { \ |
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.id = _id, \ |
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.name = _name, \ |
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.parent_name = _parent, \ |
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.regs = ð_cg_regs, \ |
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.shift = _shift, \ |
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.ops = &mtk_clk_gate_ops_no_setclr_inv, \ |
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} |
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static const struct mtk_gate eth_clks[] = { |
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GATE_ETH(CLK_ETHSYS_HSDMA, "hsdma_clk", "ethif_sel", 5), |
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GATE_ETH(CLK_ETHSYS_ESW, "esw_clk", "ethpll_500m_ck", 6), |
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GATE_ETH(CLK_ETHSYS_GP2, "gp2_clk", "trgpll", 7), |
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GATE_ETH(CLK_ETHSYS_GP1, "gp1_clk", "ethpll_500m_ck", 8), |
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GATE_ETH(CLK_ETHSYS_PCM, "pcm_clk", "ethif_sel", 11), |
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GATE_ETH(CLK_ETHSYS_GDMA, "gdma_clk", "ethif_sel", 14), |
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GATE_ETH(CLK_ETHSYS_I2S, "i2s_clk", "ethif_sel", 17), |
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GATE_ETH(CLK_ETHSYS_CRYPTO, "crypto_clk", "ethif_sel", 29), |
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}; |
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static const struct of_device_id of_match_clk_mt2701_eth[] = { |
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{ .compatible = "mediatek,mt2701-ethsys", }, |
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{} |
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}; |
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static int clk_mt2701_eth_probe(struct platform_device *pdev) |
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{ |
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struct clk_onecell_data *clk_data; |
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int r; |
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struct device_node *node = pdev->dev.of_node; |
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clk_data = mtk_alloc_clk_data(CLK_ETHSYS_NR); |
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mtk_clk_register_gates(node, eth_clks, ARRAY_SIZE(eth_clks), |
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clk_data); |
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r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); |
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if (r) |
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dev_err(&pdev->dev, |
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"could not register clock provider: %s: %d\n", |
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pdev->name, r); |
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mtk_register_reset_controller(node, 1, 0x34); |
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return r; |
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} |
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static struct platform_driver clk_mt2701_eth_drv = { |
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.probe = clk_mt2701_eth_probe, |
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.driver = { |
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.name = "clk-mt2701-eth", |
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.of_match_table = of_match_clk_mt2701_eth, |
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}, |
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}; |
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builtin_platform_driver(clk_mt2701_eth_drv);
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