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292 lines
7.2 KiB
292 lines
7.2 KiB
// SPDX-License-Identifier: GPL-2.0+ |
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// |
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// clk-max77686.c - Clock driver for Maxim 77686/MAX77802 |
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// |
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// Copyright (C) 2012 Samsung Electornics |
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// Jonghwa Lee <[email protected]> |
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#include <linux/kernel.h> |
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#include <linux/slab.h> |
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#include <linux/err.h> |
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#include <linux/module.h> |
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#include <linux/platform_device.h> |
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#include <linux/mfd/max77620.h> |
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#include <linux/mfd/max77686.h> |
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#include <linux/mfd/max77686-private.h> |
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#include <linux/clk-provider.h> |
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#include <linux/mutex.h> |
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#include <linux/clkdev.h> |
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#include <linux/of.h> |
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#include <linux/regmap.h> |
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#include <dt-bindings/clock/maxim,max77686.h> |
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#include <dt-bindings/clock/maxim,max77802.h> |
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#include <dt-bindings/clock/maxim,max77620.h> |
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#define MAX77802_CLOCK_LOW_JITTER_SHIFT 0x3 |
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enum max77686_chip_name { |
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CHIP_MAX77686, |
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CHIP_MAX77802, |
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CHIP_MAX77620, |
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}; |
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struct max77686_hw_clk_info { |
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const char *name; |
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u32 clk_reg; |
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u32 clk_enable_mask; |
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u32 flags; |
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}; |
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struct max77686_clk_init_data { |
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struct regmap *regmap; |
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struct clk_hw hw; |
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struct clk_init_data clk_idata; |
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const struct max77686_hw_clk_info *clk_info; |
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}; |
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struct max77686_clk_driver_data { |
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enum max77686_chip_name chip; |
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struct max77686_clk_init_data *max_clk_data; |
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size_t num_clks; |
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}; |
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static const struct |
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max77686_hw_clk_info max77686_hw_clks_info[MAX77686_CLKS_NUM] = { |
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[MAX77686_CLK_AP] = { |
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.name = "32khz_ap", |
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.clk_reg = MAX77686_REG_32KHZ, |
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.clk_enable_mask = BIT(MAX77686_CLK_AP), |
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}, |
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[MAX77686_CLK_CP] = { |
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.name = "32khz_cp", |
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.clk_reg = MAX77686_REG_32KHZ, |
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.clk_enable_mask = BIT(MAX77686_CLK_CP), |
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}, |
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[MAX77686_CLK_PMIC] = { |
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.name = "32khz_pmic", |
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.clk_reg = MAX77686_REG_32KHZ, |
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.clk_enable_mask = BIT(MAX77686_CLK_PMIC), |
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}, |
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}; |
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static const struct |
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max77686_hw_clk_info max77802_hw_clks_info[MAX77802_CLKS_NUM] = { |
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[MAX77802_CLK_32K_AP] = { |
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.name = "32khz_ap", |
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.clk_reg = MAX77802_REG_32KHZ, |
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.clk_enable_mask = BIT(MAX77802_CLK_32K_AP), |
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}, |
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[MAX77802_CLK_32K_CP] = { |
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.name = "32khz_cp", |
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.clk_reg = MAX77802_REG_32KHZ, |
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.clk_enable_mask = BIT(MAX77802_CLK_32K_CP), |
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}, |
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}; |
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static const struct |
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max77686_hw_clk_info max77620_hw_clks_info[MAX77620_CLKS_NUM] = { |
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[MAX77620_CLK_32K_OUT0] = { |
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.name = "32khz_out0", |
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.clk_reg = MAX77620_REG_CNFG1_32K, |
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.clk_enable_mask = MAX77620_CNFG1_32K_OUT0_EN, |
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}, |
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}; |
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static struct max77686_clk_init_data *to_max77686_clk_init_data( |
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struct clk_hw *hw) |
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{ |
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return container_of(hw, struct max77686_clk_init_data, hw); |
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} |
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static int max77686_clk_prepare(struct clk_hw *hw) |
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{ |
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struct max77686_clk_init_data *max77686 = to_max77686_clk_init_data(hw); |
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return regmap_update_bits(max77686->regmap, max77686->clk_info->clk_reg, |
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max77686->clk_info->clk_enable_mask, |
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max77686->clk_info->clk_enable_mask); |
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} |
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static void max77686_clk_unprepare(struct clk_hw *hw) |
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{ |
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struct max77686_clk_init_data *max77686 = to_max77686_clk_init_data(hw); |
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regmap_update_bits(max77686->regmap, max77686->clk_info->clk_reg, |
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max77686->clk_info->clk_enable_mask, |
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~max77686->clk_info->clk_enable_mask); |
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} |
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static int max77686_clk_is_prepared(struct clk_hw *hw) |
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{ |
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struct max77686_clk_init_data *max77686 = to_max77686_clk_init_data(hw); |
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int ret; |
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u32 val; |
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ret = regmap_read(max77686->regmap, max77686->clk_info->clk_reg, &val); |
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if (ret < 0) |
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return -EINVAL; |
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return val & max77686->clk_info->clk_enable_mask; |
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} |
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static unsigned long max77686_recalc_rate(struct clk_hw *hw, |
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unsigned long parent_rate) |
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{ |
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return 32768; |
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} |
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static const struct clk_ops max77686_clk_ops = { |
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.prepare = max77686_clk_prepare, |
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.unprepare = max77686_clk_unprepare, |
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.is_prepared = max77686_clk_is_prepared, |
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.recalc_rate = max77686_recalc_rate, |
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}; |
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static struct clk_hw * |
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of_clk_max77686_get(struct of_phandle_args *clkspec, void *data) |
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{ |
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struct max77686_clk_driver_data *drv_data = data; |
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unsigned int idx = clkspec->args[0]; |
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if (idx >= drv_data->num_clks) { |
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pr_err("%s: invalid index %u\n", __func__, idx); |
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return ERR_PTR(-EINVAL); |
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} |
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return &drv_data->max_clk_data[idx].hw; |
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} |
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static int max77686_clk_probe(struct platform_device *pdev) |
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{ |
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struct device *dev = &pdev->dev; |
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struct device *parent = dev->parent; |
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const struct platform_device_id *id = platform_get_device_id(pdev); |
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struct max77686_clk_driver_data *drv_data; |
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const struct max77686_hw_clk_info *hw_clks; |
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struct regmap *regmap; |
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int i, ret, num_clks; |
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drv_data = devm_kzalloc(dev, sizeof(*drv_data), GFP_KERNEL); |
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if (!drv_data) |
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return -ENOMEM; |
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regmap = dev_get_regmap(parent, NULL); |
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if (!regmap) { |
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dev_err(dev, "Failed to get rtc regmap\n"); |
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return -ENODEV; |
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} |
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drv_data->chip = id->driver_data; |
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switch (drv_data->chip) { |
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case CHIP_MAX77686: |
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num_clks = MAX77686_CLKS_NUM; |
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hw_clks = max77686_hw_clks_info; |
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break; |
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case CHIP_MAX77802: |
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num_clks = MAX77802_CLKS_NUM; |
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hw_clks = max77802_hw_clks_info; |
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break; |
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case CHIP_MAX77620: |
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num_clks = MAX77620_CLKS_NUM; |
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hw_clks = max77620_hw_clks_info; |
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break; |
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default: |
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dev_err(dev, "Unknown Chip ID\n"); |
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return -EINVAL; |
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} |
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drv_data->num_clks = num_clks; |
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drv_data->max_clk_data = devm_kcalloc(dev, num_clks, |
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sizeof(*drv_data->max_clk_data), |
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GFP_KERNEL); |
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if (!drv_data->max_clk_data) |
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return -ENOMEM; |
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for (i = 0; i < num_clks; i++) { |
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struct max77686_clk_init_data *max_clk_data; |
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const char *clk_name; |
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max_clk_data = &drv_data->max_clk_data[i]; |
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max_clk_data->regmap = regmap; |
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max_clk_data->clk_info = &hw_clks[i]; |
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max_clk_data->clk_idata.flags = hw_clks[i].flags; |
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max_clk_data->clk_idata.ops = &max77686_clk_ops; |
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if (parent->of_node && |
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!of_property_read_string_index(parent->of_node, |
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"clock-output-names", |
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i, &clk_name)) |
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max_clk_data->clk_idata.name = clk_name; |
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else |
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max_clk_data->clk_idata.name = hw_clks[i].name; |
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max_clk_data->hw.init = &max_clk_data->clk_idata; |
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ret = devm_clk_hw_register(dev, &max_clk_data->hw); |
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if (ret) { |
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dev_err(dev, "Failed to clock register: %d\n", ret); |
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return ret; |
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} |
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ret = devm_clk_hw_register_clkdev(dev, &max_clk_data->hw, |
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max_clk_data->clk_idata.name, |
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NULL); |
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if (ret < 0) { |
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dev_err(dev, "Failed to clkdev register: %d\n", ret); |
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return ret; |
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} |
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} |
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if (parent->of_node) { |
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ret = devm_of_clk_add_hw_provider(dev, of_clk_max77686_get, |
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drv_data); |
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if (ret < 0) { |
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dev_err(dev, "Failed to register OF clock provider: %d\n", |
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ret); |
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return ret; |
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} |
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} |
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/* MAX77802: Enable low-jitter mode on the 32khz clocks. */ |
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if (drv_data->chip == CHIP_MAX77802) { |
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ret = regmap_update_bits(regmap, MAX77802_REG_32KHZ, |
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1 << MAX77802_CLOCK_LOW_JITTER_SHIFT, |
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1 << MAX77802_CLOCK_LOW_JITTER_SHIFT); |
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if (ret < 0) { |
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dev_err(dev, "Failed to config low-jitter: %d\n", ret); |
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return ret; |
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} |
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} |
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return 0; |
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} |
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static const struct platform_device_id max77686_clk_id[] = { |
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{ "max77686-clk", .driver_data = CHIP_MAX77686, }, |
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{ "max77802-clk", .driver_data = CHIP_MAX77802, }, |
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{ "max77620-clock", .driver_data = CHIP_MAX77620, }, |
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{}, |
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}; |
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MODULE_DEVICE_TABLE(platform, max77686_clk_id); |
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static struct platform_driver max77686_clk_driver = { |
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.driver = { |
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.name = "max77686-clk", |
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}, |
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.probe = max77686_clk_probe, |
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.id_table = max77686_clk_id, |
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}; |
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module_platform_driver(max77686_clk_driver); |
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MODULE_DESCRIPTION("MAXIM 77686 Clock Driver"); |
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MODULE_AUTHOR("Jonghwa Lee <[email protected]>"); |
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MODULE_LICENSE("GPL");
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