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722 lines
19 KiB
722 lines
19 KiB
// SPDX-License-Identifier: GPL-2.0 |
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/* |
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* leon_pci_grpci1.c: GRPCI1 Host PCI driver |
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* |
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* Copyright (C) 2013 Aeroflex Gaisler AB |
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* |
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* This GRPCI1 driver does not support PCI interrupts taken from |
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* GPIO pins. Interrupt generation at PCI parity and system error |
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* detection is by default turned off since some GRPCI1 cores does |
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* not support detection. It can be turned on from the bootloader |
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* using the all_pci_errors property. |
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* |
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* Contributors: Daniel Hellstrom <[email protected]> |
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*/ |
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#include <linux/of_device.h> |
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#include <linux/export.h> |
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#include <linux/kernel.h> |
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#include <linux/of_irq.h> |
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#include <linux/delay.h> |
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#include <linux/pci.h> |
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#include <asm/leon_pci.h> |
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#include <asm/sections.h> |
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#include <asm/vaddrs.h> |
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#include <asm/leon.h> |
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#include <asm/io.h> |
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#include "irq.h" |
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/* Enable/Disable Debugging Configuration Space Access */ |
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#undef GRPCI1_DEBUG_CFGACCESS |
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/* |
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* GRPCI1 APB Register MAP |
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*/ |
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struct grpci1_regs { |
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unsigned int cfg_stat; /* 0x00 Configuration / Status */ |
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unsigned int bar0; /* 0x04 BAR0 (RO) */ |
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unsigned int page0; /* 0x08 PAGE0 (RO) */ |
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unsigned int bar1; /* 0x0C BAR1 (RO) */ |
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unsigned int page1; /* 0x10 PAGE1 */ |
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unsigned int iomap; /* 0x14 IO Map */ |
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unsigned int stat_cmd; /* 0x18 PCI Status & Command (RO) */ |
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unsigned int irq; /* 0x1C Interrupt register */ |
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}; |
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#define REGLOAD(a) (be32_to_cpu(__raw_readl(&(a)))) |
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#define REGSTORE(a, v) (__raw_writel(cpu_to_be32(v), &(a))) |
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#define PAGE0_BTEN_BIT 0 |
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#define PAGE0_BTEN (1 << PAGE0_BTEN_BIT) |
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#define CFGSTAT_HOST_BIT 13 |
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#define CFGSTAT_CTO_BIT 8 |
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#define CFGSTAT_HOST (1 << CFGSTAT_HOST_BIT) |
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#define CFGSTAT_CTO (1 << CFGSTAT_CTO_BIT) |
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#define IRQ_DPE (1 << 9) |
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#define IRQ_SSE (1 << 8) |
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#define IRQ_RMA (1 << 7) |
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#define IRQ_RTA (1 << 6) |
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#define IRQ_STA (1 << 5) |
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#define IRQ_DPED (1 << 4) |
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#define IRQ_INTD (1 << 3) |
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#define IRQ_INTC (1 << 2) |
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#define IRQ_INTB (1 << 1) |
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#define IRQ_INTA (1 << 0) |
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#define IRQ_DEF_ERRORS (IRQ_RMA | IRQ_RTA | IRQ_STA) |
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#define IRQ_ALL_ERRORS (IRQ_DPED | IRQ_DEF_ERRORS | IRQ_SSE | IRQ_DPE) |
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#define IRQ_INTX (IRQ_INTA | IRQ_INTB | IRQ_INTC | IRQ_INTD) |
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#define IRQ_MASK_BIT 16 |
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#define DEF_PCI_ERRORS (PCI_STATUS_SIG_TARGET_ABORT | \ |
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PCI_STATUS_REC_TARGET_ABORT | \ |
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PCI_STATUS_REC_MASTER_ABORT) |
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#define ALL_PCI_ERRORS (PCI_STATUS_PARITY | PCI_STATUS_DETECTED_PARITY | \ |
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PCI_STATUS_SIG_SYSTEM_ERROR | DEF_PCI_ERRORS) |
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#define TGT 256 |
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struct grpci1_priv { |
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struct leon_pci_info info; /* must be on top of this structure */ |
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struct grpci1_regs __iomem *regs; /* GRPCI register map */ |
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struct device *dev; |
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int pci_err_mask; /* STATUS register error mask */ |
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int irq; /* LEON irqctrl GRPCI IRQ */ |
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unsigned char irq_map[4]; /* GRPCI nexus PCI INTX# IRQs */ |
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unsigned int irq_err; /* GRPCI nexus Virt Error IRQ */ |
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/* AHB PCI Windows */ |
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unsigned long pci_area; /* MEMORY */ |
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unsigned long pci_area_end; |
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unsigned long pci_io; /* I/O */ |
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unsigned long pci_conf; /* CONFIGURATION */ |
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unsigned long pci_conf_end; |
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unsigned long pci_io_va; |
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}; |
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static struct grpci1_priv *grpci1priv; |
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static int grpci1_cfg_w32(struct grpci1_priv *priv, unsigned int bus, |
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unsigned int devfn, int where, u32 val); |
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static int grpci1_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) |
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{ |
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struct grpci1_priv *priv = dev->bus->sysdata; |
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int irq_group; |
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/* Use default IRQ decoding on PCI BUS0 according slot numbering */ |
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irq_group = slot & 0x3; |
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pin = ((pin - 1) + irq_group) & 0x3; |
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return priv->irq_map[pin]; |
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} |
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static int grpci1_cfg_r32(struct grpci1_priv *priv, unsigned int bus, |
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unsigned int devfn, int where, u32 *val) |
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{ |
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u32 *pci_conf, tmp, cfg; |
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if (where & 0x3) |
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return -EINVAL; |
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if (bus == 0) { |
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devfn += (0x8 * 6); /* start at AD16=Device0 */ |
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} else if (bus == TGT) { |
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bus = 0; |
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devfn = 0; /* special case: bridge controller itself */ |
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} |
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/* Select bus */ |
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cfg = REGLOAD(priv->regs->cfg_stat); |
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REGSTORE(priv->regs->cfg_stat, (cfg & ~(0xf << 23)) | (bus << 23)); |
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/* do read access */ |
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pci_conf = (u32 *) (priv->pci_conf | (devfn << 8) | (where & 0xfc)); |
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tmp = LEON3_BYPASS_LOAD_PA(pci_conf); |
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/* check if master abort was received */ |
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if (REGLOAD(priv->regs->cfg_stat) & CFGSTAT_CTO) { |
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*val = 0xffffffff; |
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/* Clear Master abort bit in PCI cfg space (is set) */ |
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tmp = REGLOAD(priv->regs->stat_cmd); |
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grpci1_cfg_w32(priv, TGT, 0, PCI_COMMAND, tmp); |
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} else { |
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/* Bus always little endian (unaffected by byte-swapping) */ |
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*val = swab32(tmp); |
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} |
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return 0; |
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} |
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static int grpci1_cfg_r16(struct grpci1_priv *priv, unsigned int bus, |
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unsigned int devfn, int where, u32 *val) |
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{ |
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u32 v; |
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int ret; |
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if (where & 0x1) |
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return -EINVAL; |
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ret = grpci1_cfg_r32(priv, bus, devfn, where & ~0x3, &v); |
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*val = 0xffff & (v >> (8 * (where & 0x3))); |
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return ret; |
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} |
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static int grpci1_cfg_r8(struct grpci1_priv *priv, unsigned int bus, |
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unsigned int devfn, int where, u32 *val) |
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{ |
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u32 v; |
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int ret; |
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ret = grpci1_cfg_r32(priv, bus, devfn, where & ~0x3, &v); |
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*val = 0xff & (v >> (8 * (where & 3))); |
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return ret; |
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} |
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static int grpci1_cfg_w32(struct grpci1_priv *priv, unsigned int bus, |
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unsigned int devfn, int where, u32 val) |
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{ |
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unsigned int *pci_conf; |
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u32 cfg; |
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if (where & 0x3) |
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return -EINVAL; |
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if (bus == 0) { |
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devfn += (0x8 * 6); /* start at AD16=Device0 */ |
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} else if (bus == TGT) { |
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bus = 0; |
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devfn = 0; /* special case: bridge controller itself */ |
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} |
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/* Select bus */ |
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cfg = REGLOAD(priv->regs->cfg_stat); |
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REGSTORE(priv->regs->cfg_stat, (cfg & ~(0xf << 23)) | (bus << 23)); |
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pci_conf = (unsigned int *) (priv->pci_conf | |
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(devfn << 8) | (where & 0xfc)); |
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LEON3_BYPASS_STORE_PA(pci_conf, swab32(val)); |
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return 0; |
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} |
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static int grpci1_cfg_w16(struct grpci1_priv *priv, unsigned int bus, |
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unsigned int devfn, int where, u32 val) |
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{ |
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int ret; |
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u32 v; |
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if (where & 0x1) |
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return -EINVAL; |
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ret = grpci1_cfg_r32(priv, bus, devfn, where&~3, &v); |
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if (ret) |
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return ret; |
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v = (v & ~(0xffff << (8 * (where & 0x3)))) | |
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((0xffff & val) << (8 * (where & 0x3))); |
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return grpci1_cfg_w32(priv, bus, devfn, where & ~0x3, v); |
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} |
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static int grpci1_cfg_w8(struct grpci1_priv *priv, unsigned int bus, |
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unsigned int devfn, int where, u32 val) |
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{ |
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int ret; |
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u32 v; |
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ret = grpci1_cfg_r32(priv, bus, devfn, where & ~0x3, &v); |
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if (ret != 0) |
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return ret; |
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v = (v & ~(0xff << (8 * (where & 0x3)))) | |
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((0xff & val) << (8 * (where & 0x3))); |
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return grpci1_cfg_w32(priv, bus, devfn, where & ~0x3, v); |
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} |
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/* Read from Configuration Space. When entering here the PCI layer has taken |
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* the pci_lock spinlock and IRQ is off. |
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*/ |
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static int grpci1_read_config(struct pci_bus *bus, unsigned int devfn, |
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int where, int size, u32 *val) |
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{ |
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struct grpci1_priv *priv = grpci1priv; |
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unsigned int busno = bus->number; |
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int ret; |
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if (PCI_SLOT(devfn) > 15 || busno > 15) { |
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*val = ~0; |
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return 0; |
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} |
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switch (size) { |
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case 1: |
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ret = grpci1_cfg_r8(priv, busno, devfn, where, val); |
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break; |
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case 2: |
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ret = grpci1_cfg_r16(priv, busno, devfn, where, val); |
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break; |
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case 4: |
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ret = grpci1_cfg_r32(priv, busno, devfn, where, val); |
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break; |
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default: |
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ret = -EINVAL; |
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break; |
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} |
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#ifdef GRPCI1_DEBUG_CFGACCESS |
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printk(KERN_INFO |
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"grpci1_read_config: [%02x:%02x:%x] ofs=%d val=%x size=%d\n", |
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busno, PCI_SLOT(devfn), PCI_FUNC(devfn), where, *val, size); |
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#endif |
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return ret; |
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} |
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/* Write to Configuration Space. When entering here the PCI layer has taken |
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* the pci_lock spinlock and IRQ is off. |
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*/ |
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static int grpci1_write_config(struct pci_bus *bus, unsigned int devfn, |
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int where, int size, u32 val) |
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{ |
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struct grpci1_priv *priv = grpci1priv; |
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unsigned int busno = bus->number; |
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if (PCI_SLOT(devfn) > 15 || busno > 15) |
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return 0; |
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#ifdef GRPCI1_DEBUG_CFGACCESS |
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printk(KERN_INFO |
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"grpci1_write_config: [%02x:%02x:%x] ofs=%d size=%d val=%x\n", |
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busno, PCI_SLOT(devfn), PCI_FUNC(devfn), where, size, val); |
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#endif |
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switch (size) { |
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default: |
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return -EINVAL; |
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case 1: |
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return grpci1_cfg_w8(priv, busno, devfn, where, val); |
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case 2: |
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return grpci1_cfg_w16(priv, busno, devfn, where, val); |
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case 4: |
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return grpci1_cfg_w32(priv, busno, devfn, where, val); |
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} |
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} |
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static struct pci_ops grpci1_ops = { |
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.read = grpci1_read_config, |
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.write = grpci1_write_config, |
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}; |
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/* GENIRQ IRQ chip implementation for grpci1 irqmode=0..2. In configuration |
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* 3 where all PCI Interrupts has a separate IRQ on the system IRQ controller |
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* this is not needed and the standard IRQ controller can be used. |
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*/ |
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static void grpci1_mask_irq(struct irq_data *data) |
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{ |
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u32 irqidx; |
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struct grpci1_priv *priv = grpci1priv; |
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irqidx = (u32)data->chip_data - 1; |
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if (irqidx > 3) /* only mask PCI interrupts here */ |
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return; |
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irqidx += IRQ_MASK_BIT; |
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REGSTORE(priv->regs->irq, REGLOAD(priv->regs->irq) & ~(1 << irqidx)); |
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} |
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static void grpci1_unmask_irq(struct irq_data *data) |
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{ |
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u32 irqidx; |
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struct grpci1_priv *priv = grpci1priv; |
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irqidx = (u32)data->chip_data - 1; |
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if (irqidx > 3) /* only unmask PCI interrupts here */ |
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return; |
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irqidx += IRQ_MASK_BIT; |
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REGSTORE(priv->regs->irq, REGLOAD(priv->regs->irq) | (1 << irqidx)); |
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} |
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static unsigned int grpci1_startup_irq(struct irq_data *data) |
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{ |
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grpci1_unmask_irq(data); |
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return 0; |
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} |
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static void grpci1_shutdown_irq(struct irq_data *data) |
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{ |
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grpci1_mask_irq(data); |
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} |
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static struct irq_chip grpci1_irq = { |
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.name = "grpci1", |
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.irq_startup = grpci1_startup_irq, |
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.irq_shutdown = grpci1_shutdown_irq, |
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.irq_mask = grpci1_mask_irq, |
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.irq_unmask = grpci1_unmask_irq, |
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}; |
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/* Handle one or multiple IRQs from the PCI core */ |
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static void grpci1_pci_flow_irq(struct irq_desc *desc) |
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{ |
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struct grpci1_priv *priv = grpci1priv; |
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int i, ack = 0; |
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unsigned int irqreg; |
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irqreg = REGLOAD(priv->regs->irq); |
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irqreg = (irqreg >> IRQ_MASK_BIT) & irqreg; |
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/* Error Interrupt? */ |
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if (irqreg & IRQ_ALL_ERRORS) { |
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generic_handle_irq(priv->irq_err); |
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ack = 1; |
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} |
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/* PCI Interrupt? */ |
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if (irqreg & IRQ_INTX) { |
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/* Call respective PCI Interrupt handler */ |
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for (i = 0; i < 4; i++) { |
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if (irqreg & (1 << i)) |
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generic_handle_irq(priv->irq_map[i]); |
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} |
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ack = 1; |
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} |
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/* |
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* Call "first level" IRQ chip end-of-irq handler. It will ACK LEON IRQ |
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* Controller, this must be done after IRQ sources have been handled to |
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* avoid double IRQ generation |
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*/ |
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if (ack) |
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desc->irq_data.chip->irq_eoi(&desc->irq_data); |
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} |
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/* Create a virtual IRQ */ |
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static unsigned int grpci1_build_device_irq(unsigned int irq) |
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{ |
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unsigned int virq = 0, pil; |
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pil = 1 << 8; |
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virq = irq_alloc(irq, pil); |
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if (virq == 0) |
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goto out; |
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irq_set_chip_and_handler_name(virq, &grpci1_irq, handle_simple_irq, |
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"pcilvl"); |
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irq_set_chip_data(virq, (void *)irq); |
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out: |
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return virq; |
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} |
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/* |
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* Initialize mappings AMBA<->PCI, clear IRQ state, setup PCI interface |
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* |
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* Target BARs: |
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* BAR0: unused in this implementation |
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* BAR1: peripheral DMA to host's memory (size at least 256MByte) |
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* BAR2..BAR5: not implemented in hardware |
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*/ |
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static void grpci1_hw_init(struct grpci1_priv *priv) |
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{ |
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u32 ahbadr, bar_sz, data, pciadr; |
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struct grpci1_regs __iomem *regs = priv->regs; |
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/* set 1:1 mapping between AHB -> PCI memory space */ |
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REGSTORE(regs->cfg_stat, priv->pci_area & 0xf0000000); |
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/* map PCI accesses to target BAR1 to Linux kernel memory 1:1 */ |
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ahbadr = 0xf0000000 & (u32)__pa(PAGE_ALIGN((unsigned long) &_end)); |
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REGSTORE(regs->page1, ahbadr); |
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/* translate I/O accesses to 0, I/O Space always @ PCI low 64Kbytes */ |
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REGSTORE(regs->iomap, REGLOAD(regs->iomap) & 0x0000ffff); |
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/* disable and clear pending interrupts */ |
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REGSTORE(regs->irq, 0); |
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/* Setup BAR0 outside access range so that it does not conflict with |
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* peripheral DMA. There is no need to set up the PAGE0 register. |
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*/ |
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grpci1_cfg_w32(priv, TGT, 0, PCI_BASE_ADDRESS_0, 0xffffffff); |
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grpci1_cfg_r32(priv, TGT, 0, PCI_BASE_ADDRESS_0, &bar_sz); |
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bar_sz = ~bar_sz + 1; |
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pciadr = priv->pci_area - bar_sz; |
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grpci1_cfg_w32(priv, TGT, 0, PCI_BASE_ADDRESS_0, pciadr); |
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/* |
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* Setup the Host's PCI Target BAR1 for other peripherals to access, |
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* and do DMA to the host's memory. |
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*/ |
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grpci1_cfg_w32(priv, TGT, 0, PCI_BASE_ADDRESS_1, ahbadr); |
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/* |
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* Setup Latency Timer and cache line size. Default cache line |
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* size will result in poor performance (256 word fetches), 0xff |
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* will set it according to the max size of the PCI FIFO. |
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*/ |
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grpci1_cfg_w8(priv, TGT, 0, PCI_CACHE_LINE_SIZE, 0xff); |
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grpci1_cfg_w8(priv, TGT, 0, PCI_LATENCY_TIMER, 0x40); |
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/* set as bus master, enable pci memory responses, clear status bits */ |
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grpci1_cfg_r32(priv, TGT, 0, PCI_COMMAND, &data); |
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data |= (PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); |
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grpci1_cfg_w32(priv, TGT, 0, PCI_COMMAND, data); |
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} |
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static irqreturn_t grpci1_jump_interrupt(int irq, void *arg) |
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{ |
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struct grpci1_priv *priv = arg; |
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dev_err(priv->dev, "Jump IRQ happened\n"); |
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return IRQ_NONE; |
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} |
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/* Handle GRPCI1 Error Interrupt */ |
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static irqreturn_t grpci1_err_interrupt(int irq, void *arg) |
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{ |
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struct grpci1_priv *priv = arg; |
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u32 status; |
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grpci1_cfg_r16(priv, TGT, 0, PCI_STATUS, &status); |
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status &= priv->pci_err_mask; |
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if (status == 0) |
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return IRQ_NONE; |
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if (status & PCI_STATUS_PARITY) |
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dev_err(priv->dev, "Data Parity Error\n"); |
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if (status & PCI_STATUS_SIG_TARGET_ABORT) |
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dev_err(priv->dev, "Signalled Target Abort\n"); |
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if (status & PCI_STATUS_REC_TARGET_ABORT) |
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dev_err(priv->dev, "Received Target Abort\n"); |
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if (status & PCI_STATUS_REC_MASTER_ABORT) |
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dev_err(priv->dev, "Received Master Abort\n"); |
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if (status & PCI_STATUS_SIG_SYSTEM_ERROR) |
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dev_err(priv->dev, "Signalled System Error\n"); |
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if (status & PCI_STATUS_DETECTED_PARITY) |
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dev_err(priv->dev, "Parity Error\n"); |
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/* Clear handled INT TYPE IRQs */ |
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grpci1_cfg_w16(priv, TGT, 0, PCI_STATUS, status); |
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return IRQ_HANDLED; |
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} |
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static int grpci1_of_probe(struct platform_device *ofdev) |
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{ |
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struct grpci1_regs __iomem *regs; |
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struct grpci1_priv *priv; |
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int err, len; |
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const int *tmp; |
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u32 cfg, size, err_mask; |
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struct resource *res; |
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if (grpci1priv) { |
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dev_err(&ofdev->dev, "only one GRPCI1 supported\n"); |
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return -ENODEV; |
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} |
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if (ofdev->num_resources < 3) { |
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dev_err(&ofdev->dev, "not enough APB/AHB resources\n"); |
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return -EIO; |
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} |
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priv = devm_kzalloc(&ofdev->dev, sizeof(*priv), GFP_KERNEL); |
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if (!priv) { |
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dev_err(&ofdev->dev, "memory allocation failed\n"); |
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return -ENOMEM; |
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} |
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platform_set_drvdata(ofdev, priv); |
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priv->dev = &ofdev->dev; |
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|
|
/* find device register base address */ |
|
res = platform_get_resource(ofdev, IORESOURCE_MEM, 0); |
|
regs = devm_ioremap_resource(&ofdev->dev, res); |
|
if (IS_ERR(regs)) |
|
return PTR_ERR(regs); |
|
|
|
/* |
|
* check that we're in Host Slot and that we can act as a Host Bridge |
|
* and not only as target/peripheral. |
|
*/ |
|
cfg = REGLOAD(regs->cfg_stat); |
|
if ((cfg & CFGSTAT_HOST) == 0) { |
|
dev_err(&ofdev->dev, "not in host system slot\n"); |
|
return -EIO; |
|
} |
|
|
|
/* check that BAR1 support 256 MByte so that we can map kernel space */ |
|
REGSTORE(regs->page1, 0xffffffff); |
|
size = ~REGLOAD(regs->page1) + 1; |
|
if (size < 0x10000000) { |
|
dev_err(&ofdev->dev, "BAR1 must be at least 256MByte\n"); |
|
return -EIO; |
|
} |
|
|
|
/* hardware must support little-endian PCI (byte-twisting) */ |
|
if ((REGLOAD(regs->page0) & PAGE0_BTEN) == 0) { |
|
dev_err(&ofdev->dev, "byte-twisting is required\n"); |
|
return -EIO; |
|
} |
|
|
|
priv->regs = regs; |
|
priv->irq = irq_of_parse_and_map(ofdev->dev.of_node, 0); |
|
dev_info(&ofdev->dev, "host found at 0x%p, irq%d\n", regs, priv->irq); |
|
|
|
/* Find PCI Memory, I/O and Configuration Space Windows */ |
|
priv->pci_area = ofdev->resource[1].start; |
|
priv->pci_area_end = ofdev->resource[1].end+1; |
|
priv->pci_io = ofdev->resource[2].start; |
|
priv->pci_conf = ofdev->resource[2].start + 0x10000; |
|
priv->pci_conf_end = priv->pci_conf + 0x10000; |
|
priv->pci_io_va = (unsigned long)ioremap(priv->pci_io, 0x10000); |
|
if (!priv->pci_io_va) { |
|
dev_err(&ofdev->dev, "unable to map PCI I/O area\n"); |
|
return -EIO; |
|
} |
|
|
|
printk(KERN_INFO |
|
"GRPCI1: MEMORY SPACE [0x%08lx - 0x%08lx]\n" |
|
" I/O SPACE [0x%08lx - 0x%08lx]\n" |
|
" CONFIG SPACE [0x%08lx - 0x%08lx]\n", |
|
priv->pci_area, priv->pci_area_end-1, |
|
priv->pci_io, priv->pci_conf-1, |
|
priv->pci_conf, priv->pci_conf_end-1); |
|
|
|
/* |
|
* I/O Space resources in I/O Window mapped into Virtual Adr Space |
|
* We never use low 4KB because some devices seem have problems using |
|
* address 0. |
|
*/ |
|
priv->info.io_space.name = "GRPCI1 PCI I/O Space"; |
|
priv->info.io_space.start = priv->pci_io_va + 0x1000; |
|
priv->info.io_space.end = priv->pci_io_va + 0x10000 - 1; |
|
priv->info.io_space.flags = IORESOURCE_IO; |
|
|
|
/* |
|
* grpci1 has no prefetchable memory, map everything as |
|
* non-prefetchable memory |
|
*/ |
|
priv->info.mem_space.name = "GRPCI1 PCI MEM Space"; |
|
priv->info.mem_space.start = priv->pci_area; |
|
priv->info.mem_space.end = priv->pci_area_end - 1; |
|
priv->info.mem_space.flags = IORESOURCE_MEM; |
|
|
|
if (request_resource(&iomem_resource, &priv->info.mem_space) < 0) { |
|
dev_err(&ofdev->dev, "unable to request PCI memory area\n"); |
|
err = -ENOMEM; |
|
goto err1; |
|
} |
|
|
|
if (request_resource(&ioport_resource, &priv->info.io_space) < 0) { |
|
dev_err(&ofdev->dev, "unable to request PCI I/O area\n"); |
|
err = -ENOMEM; |
|
goto err2; |
|
} |
|
|
|
/* setup maximum supported PCI buses */ |
|
priv->info.busn.name = "GRPCI1 busn"; |
|
priv->info.busn.start = 0; |
|
priv->info.busn.end = 15; |
|
|
|
grpci1priv = priv; |
|
|
|
/* Initialize hardware */ |
|
grpci1_hw_init(priv); |
|
|
|
/* |
|
* Get PCI Interrupt to System IRQ mapping and setup IRQ handling |
|
* Error IRQ. All PCI and PCI-Error interrupts are shared using the |
|
* same system IRQ. |
|
*/ |
|
leon_update_virq_handling(priv->irq, grpci1_pci_flow_irq, "pcilvl", 0); |
|
|
|
priv->irq_map[0] = grpci1_build_device_irq(1); |
|
priv->irq_map[1] = grpci1_build_device_irq(2); |
|
priv->irq_map[2] = grpci1_build_device_irq(3); |
|
priv->irq_map[3] = grpci1_build_device_irq(4); |
|
priv->irq_err = grpci1_build_device_irq(5); |
|
|
|
printk(KERN_INFO " PCI INTA..D#: IRQ%d, IRQ%d, IRQ%d, IRQ%d\n", |
|
priv->irq_map[0], priv->irq_map[1], priv->irq_map[2], |
|
priv->irq_map[3]); |
|
|
|
/* Enable IRQs on LEON IRQ controller */ |
|
err = devm_request_irq(&ofdev->dev, priv->irq, grpci1_jump_interrupt, 0, |
|
"GRPCI1_JUMP", priv); |
|
if (err) { |
|
dev_err(&ofdev->dev, "ERR IRQ request failed: %d\n", err); |
|
goto err3; |
|
} |
|
|
|
/* Setup IRQ handler for access errors */ |
|
err = devm_request_irq(&ofdev->dev, priv->irq_err, |
|
grpci1_err_interrupt, IRQF_SHARED, "GRPCI1_ERR", |
|
priv); |
|
if (err) { |
|
dev_err(&ofdev->dev, "ERR VIRQ request failed: %d\n", err); |
|
goto err3; |
|
} |
|
|
|
tmp = of_get_property(ofdev->dev.of_node, "all_pci_errors", &len); |
|
if (tmp && (len == 4)) { |
|
priv->pci_err_mask = ALL_PCI_ERRORS; |
|
err_mask = IRQ_ALL_ERRORS << IRQ_MASK_BIT; |
|
} else { |
|
priv->pci_err_mask = DEF_PCI_ERRORS; |
|
err_mask = IRQ_DEF_ERRORS << IRQ_MASK_BIT; |
|
} |
|
|
|
/* |
|
* Enable Error Interrupts. PCI interrupts are unmasked once request_irq |
|
* is called by the PCI Device drivers |
|
*/ |
|
REGSTORE(regs->irq, err_mask); |
|
|
|
/* Init common layer and scan buses */ |
|
priv->info.ops = &grpci1_ops; |
|
priv->info.map_irq = grpci1_map_irq; |
|
leon_pci_init(ofdev, &priv->info); |
|
|
|
return 0; |
|
|
|
err3: |
|
release_resource(&priv->info.io_space); |
|
err2: |
|
release_resource(&priv->info.mem_space); |
|
err1: |
|
iounmap((void __iomem *)priv->pci_io_va); |
|
grpci1priv = NULL; |
|
return err; |
|
} |
|
|
|
static const struct of_device_id grpci1_of_match[] __initconst = { |
|
{ |
|
.name = "GAISLER_PCIFBRG", |
|
}, |
|
{ |
|
.name = "01_014", |
|
}, |
|
{}, |
|
}; |
|
|
|
static struct platform_driver grpci1_of_driver = { |
|
.driver = { |
|
.name = "grpci1", |
|
.of_match_table = grpci1_of_match, |
|
}, |
|
.probe = grpci1_of_probe, |
|
}; |
|
|
|
static int __init grpci1_init(void) |
|
{ |
|
return platform_driver_register(&grpci1_of_driver); |
|
} |
|
|
|
subsys_initcall(grpci1_init);
|
|
|