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121 lines
3.0 KiB
121 lines
3.0 KiB
// SPDX-License-Identifier: GPL-2.0-only |
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/* |
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* NVIDIA Tegra SoC device tree board support |
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* |
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* Copyright (C) 2011, 2013, NVIDIA Corporation |
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* Copyright (C) 2010 Secret Lab Technologies, Ltd. |
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* Copyright (C) 2010 Google, Inc. |
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*/ |
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#include <linux/clk.h> |
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#include <linux/clk/tegra.h> |
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#include <linux/dma-mapping.h> |
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#include <linux/init.h> |
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#include <linux/io.h> |
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#include <linux/irqchip.h> |
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#include <linux/irqdomain.h> |
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#include <linux/kernel.h> |
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#include <linux/of_address.h> |
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#include <linux/of_fdt.h> |
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#include <linux/of.h> |
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#include <linux/of_platform.h> |
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#include <linux/pda_power.h> |
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#include <linux/platform_device.h> |
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#include <linux/serial_8250.h> |
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#include <linux/slab.h> |
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#include <linux/sys_soc.h> |
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#include <linux/usb/tegra_usb_phy.h> |
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#include <linux/firmware/trusted_foundations.h> |
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#include <soc/tegra/fuse.h> |
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#include <soc/tegra/pmc.h> |
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#include <asm/firmware.h> |
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#include <asm/hardware/cache-l2x0.h> |
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#include <asm/mach/arch.h> |
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#include <asm/mach/time.h> |
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#include <asm/mach-types.h> |
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#include <asm/psci.h> |
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#include <asm/setup.h> |
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#include "board.h" |
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#include "common.h" |
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#include "iomap.h" |
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#include "pm.h" |
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#include "reset.h" |
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#include "sleep.h" |
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/* |
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* Storage for debug-macro.S's state. |
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* |
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* This must be in .data not .bss so that it gets initialized each time the |
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* kernel is loaded. The data is declared here rather than debug-macro.S so |
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* that multiple inclusions of debug-macro.S point at the same data. |
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*/ |
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u32 tegra_uart_config[3] = { |
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/* Debug UART initialization required */ |
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1, |
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/* Debug UART physical address */ |
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0, |
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/* Debug UART virtual address */ |
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0, |
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}; |
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static void __init tegra_init_early(void) |
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{ |
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of_register_trusted_foundations(); |
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tegra_cpu_reset_handler_init(); |
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call_firmware_op(l2x0_init); |
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} |
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static void __init tegra_dt_init_irq(void) |
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{ |
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tegra_init_irq(); |
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irqchip_init(); |
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} |
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static void __init tegra_dt_init(void) |
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{ |
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struct device *parent = tegra_soc_device_register(); |
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of_platform_default_populate(NULL, NULL, parent); |
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} |
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static void __init tegra_dt_init_late(void) |
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{ |
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if (IS_ENABLED(CONFIG_ARCH_TEGRA_2x_SOC) && |
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of_machine_is_compatible("compal,paz00")) |
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tegra_paz00_wifikill_init(); |
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if (IS_ENABLED(CONFIG_ARCH_TEGRA_2x_SOC) && |
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of_machine_is_compatible("nvidia,tegra20")) |
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platform_device_register_simple("tegra20-cpufreq", -1, NULL, 0); |
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if (IS_ENABLED(CONFIG_ARM_TEGRA_CPUIDLE) && !psci_smp_available()) |
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platform_device_register_simple("tegra-cpuidle", -1, NULL, 0); |
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if (IS_ENABLED(CONFIG_ARCH_TEGRA_3x_SOC) && |
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of_machine_is_compatible("nvidia,tegra30")) |
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platform_device_register_simple("tegra20-cpufreq", -1, NULL, 0); |
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} |
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static const char * const tegra_dt_board_compat[] = { |
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"nvidia,tegra124", |
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"nvidia,tegra114", |
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"nvidia,tegra30", |
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"nvidia,tegra20", |
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NULL |
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}; |
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DT_MACHINE_START(TEGRA_DT, "NVIDIA Tegra SoC (Flattened Device Tree)") |
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.l2c_aux_val = 0x3c400000, |
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.l2c_aux_mask = 0xc20fc3ff, |
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.smp = smp_ops(tegra_smp_ops), |
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.map_io = tegra_map_common_io, |
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.init_early = tegra_init_early, |
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.init_irq = tegra_dt_init_irq, |
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.init_machine = tegra_dt_init, |
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.init_late = tegra_dt_init_late, |
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.dt_compat = tegra_dt_board_compat, |
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MACHINE_END
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