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497 lines
12 KiB
497 lines
12 KiB
/* SPDX-License-Identifier: GPL-2.0-only */ |
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/* |
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* Copyright (C) ST-Ericsson SA 2012 |
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* |
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* Author: Ola Lilja <[email protected]>, |
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* for ST-Ericsson. |
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*/ |
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#ifndef UX500_MSP_I2S_H |
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#define UX500_MSP_I2S_H |
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#include <linux/platform_device.h> |
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#include <linux/platform_data/asoc-ux500-msp.h> |
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#define MSP_INPUT_FREQ_APB 48000000 |
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/*** Stereo mode. Used for APB data accesses as 16 bits accesses (mono), |
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* 32 bits accesses (stereo). |
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***/ |
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enum msp_stereo_mode { |
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MSP_MONO, |
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MSP_STEREO |
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}; |
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/* Direction (Transmit/Receive mode) */ |
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enum msp_direction { |
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MSP_TX = 1, |
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MSP_RX = 2 |
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}; |
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/* Transmit and receive configuration register */ |
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#define MSP_BIG_ENDIAN 0x00000000 |
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#define MSP_LITTLE_ENDIAN 0x00001000 |
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#define MSP_UNEXPECTED_FS_ABORT 0x00000000 |
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#define MSP_UNEXPECTED_FS_IGNORE 0x00008000 |
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#define MSP_NON_MODE_BIT_MASK 0x00009000 |
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/* Global configuration register */ |
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#define RX_ENABLE 0x00000001 |
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#define RX_FIFO_ENABLE 0x00000002 |
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#define RX_SYNC_SRG 0x00000010 |
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#define RX_CLK_POL_RISING 0x00000020 |
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#define RX_CLK_SEL_SRG 0x00000040 |
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#define TX_ENABLE 0x00000100 |
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#define TX_FIFO_ENABLE 0x00000200 |
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#define TX_SYNC_SRG_PROG 0x00001800 |
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#define TX_SYNC_SRG_AUTO 0x00001000 |
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#define TX_CLK_POL_RISING 0x00002000 |
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#define TX_CLK_SEL_SRG 0x00004000 |
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#define TX_EXTRA_DELAY_ENABLE 0x00008000 |
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#define SRG_ENABLE 0x00010000 |
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#define FRAME_GEN_ENABLE 0x00100000 |
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#define SRG_CLK_SEL_APB 0x00000000 |
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#define RX_FIFO_SYNC_HI 0x00000000 |
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#define TX_FIFO_SYNC_HI 0x00000000 |
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#define SPI_CLK_MODE_NORMAL 0x00000000 |
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#define MSP_FRAME_SIZE_AUTO -1 |
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#define MSP_DR 0x00 |
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#define MSP_GCR 0x04 |
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#define MSP_TCF 0x08 |
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#define MSP_RCF 0x0c |
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#define MSP_SRG 0x10 |
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#define MSP_FLR 0x14 |
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#define MSP_DMACR 0x18 |
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#define MSP_IMSC 0x20 |
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#define MSP_RIS 0x24 |
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#define MSP_MIS 0x28 |
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#define MSP_ICR 0x2c |
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#define MSP_MCR 0x30 |
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#define MSP_RCV 0x34 |
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#define MSP_RCM 0x38 |
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#define MSP_TCE0 0x40 |
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#define MSP_TCE1 0x44 |
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#define MSP_TCE2 0x48 |
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#define MSP_TCE3 0x4c |
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#define MSP_RCE0 0x60 |
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#define MSP_RCE1 0x64 |
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#define MSP_RCE2 0x68 |
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#define MSP_RCE3 0x6c |
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#define MSP_IODLY 0x70 |
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#define MSP_ITCR 0x80 |
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#define MSP_ITIP 0x84 |
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#define MSP_ITOP 0x88 |
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#define MSP_TSTDR 0x8c |
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#define MSP_PID0 0xfe0 |
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#define MSP_PID1 0xfe4 |
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#define MSP_PID2 0xfe8 |
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#define MSP_PID3 0xfec |
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#define MSP_CID0 0xff0 |
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#define MSP_CID1 0xff4 |
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#define MSP_CID2 0xff8 |
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#define MSP_CID3 0xffc |
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/* Protocol dependant parameters list */ |
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#define RX_ENABLE_MASK BIT(0) |
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#define RX_FIFO_ENABLE_MASK BIT(1) |
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#define RX_FSYNC_MASK BIT(2) |
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#define DIRECT_COMPANDING_MASK BIT(3) |
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#define RX_SYNC_SEL_MASK BIT(4) |
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#define RX_CLK_POL_MASK BIT(5) |
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#define RX_CLK_SEL_MASK BIT(6) |
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#define LOOPBACK_MASK BIT(7) |
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#define TX_ENABLE_MASK BIT(8) |
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#define TX_FIFO_ENABLE_MASK BIT(9) |
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#define TX_FSYNC_MASK BIT(10) |
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#define TX_MSP_TDR_TSR BIT(11) |
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#define TX_SYNC_SEL_MASK (BIT(12) | BIT(11)) |
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#define TX_CLK_POL_MASK BIT(13) |
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#define TX_CLK_SEL_MASK BIT(14) |
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#define TX_EXTRA_DELAY_MASK BIT(15) |
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#define SRG_ENABLE_MASK BIT(16) |
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#define SRG_CLK_POL_MASK BIT(17) |
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#define SRG_CLK_SEL_MASK (BIT(19) | BIT(18)) |
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#define FRAME_GEN_EN_MASK BIT(20) |
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#define SPI_CLK_MODE_MASK (BIT(22) | BIT(21)) |
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#define SPI_BURST_MODE_MASK BIT(23) |
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#define RXEN_SHIFT 0 |
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#define RFFEN_SHIFT 1 |
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#define RFSPOL_SHIFT 2 |
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#define DCM_SHIFT 3 |
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#define RFSSEL_SHIFT 4 |
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#define RCKPOL_SHIFT 5 |
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#define RCKSEL_SHIFT 6 |
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#define LBM_SHIFT 7 |
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#define TXEN_SHIFT 8 |
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#define TFFEN_SHIFT 9 |
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#define TFSPOL_SHIFT 10 |
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#define TFSSEL_SHIFT 11 |
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#define TCKPOL_SHIFT 13 |
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#define TCKSEL_SHIFT 14 |
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#define TXDDL_SHIFT 15 |
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#define SGEN_SHIFT 16 |
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#define SCKPOL_SHIFT 17 |
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#define SCKSEL_SHIFT 18 |
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#define FGEN_SHIFT 20 |
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#define SPICKM_SHIFT 21 |
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#define TBSWAP_SHIFT 28 |
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#define RCKPOL_MASK BIT(0) |
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#define TCKPOL_MASK BIT(0) |
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#define SPICKM_MASK (BIT(1) | BIT(0)) |
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#define MSP_RX_CLKPOL_BIT(n) ((n & RCKPOL_MASK) << RCKPOL_SHIFT) |
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#define MSP_TX_CLKPOL_BIT(n) ((n & TCKPOL_MASK) << TCKPOL_SHIFT) |
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#define P1ELEN_SHIFT 0 |
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#define P1FLEN_SHIFT 3 |
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#define DTYP_SHIFT 10 |
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#define ENDN_SHIFT 12 |
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#define DDLY_SHIFT 13 |
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#define FSIG_SHIFT 15 |
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#define P2ELEN_SHIFT 16 |
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#define P2FLEN_SHIFT 19 |
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#define P2SM_SHIFT 26 |
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#define P2EN_SHIFT 27 |
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#define FSYNC_SHIFT 15 |
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#define P1ELEN_MASK 0x00000007 |
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#define P2ELEN_MASK 0x00070000 |
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#define P1FLEN_MASK 0x00000378 |
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#define P2FLEN_MASK 0x03780000 |
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#define DDLY_MASK 0x00003000 |
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#define DTYP_MASK 0x00000600 |
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#define P2SM_MASK 0x04000000 |
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#define P2EN_MASK 0x08000000 |
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#define ENDN_MASK 0x00001000 |
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#define TFSPOL_MASK 0x00000400 |
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#define TBSWAP_MASK 0x30000000 |
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#define COMPANDING_MODE_MASK 0x00000c00 |
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#define FSYNC_MASK 0x00008000 |
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#define MSP_P1_ELEM_LEN_BITS(n) (n & P1ELEN_MASK) |
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#define MSP_P2_ELEM_LEN_BITS(n) (((n) << P2ELEN_SHIFT) & P2ELEN_MASK) |
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#define MSP_P1_FRAME_LEN_BITS(n) (((n) << P1FLEN_SHIFT) & P1FLEN_MASK) |
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#define MSP_P2_FRAME_LEN_BITS(n) (((n) << P2FLEN_SHIFT) & P2FLEN_MASK) |
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#define MSP_DATA_DELAY_BITS(n) (((n) << DDLY_SHIFT) & DDLY_MASK) |
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#define MSP_DATA_TYPE_BITS(n) (((n) << DTYP_SHIFT) & DTYP_MASK) |
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#define MSP_P2_START_MODE_BIT(n) ((n << P2SM_SHIFT) & P2SM_MASK) |
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#define MSP_P2_ENABLE_BIT(n) ((n << P2EN_SHIFT) & P2EN_MASK) |
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#define MSP_SET_ENDIANNES_BIT(n) ((n << ENDN_SHIFT) & ENDN_MASK) |
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#define MSP_FSYNC_POL(n) ((n << TFSPOL_SHIFT) & TFSPOL_MASK) |
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#define MSP_DATA_WORD_SWAP(n) ((n << TBSWAP_SHIFT) & TBSWAP_MASK) |
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#define MSP_SET_COMPANDING_MODE(n) ((n << DTYP_SHIFT) & \ |
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COMPANDING_MODE_MASK) |
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#define MSP_SET_FSYNC_IGNORE(n) ((n << FSYNC_SHIFT) & FSYNC_MASK) |
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/* Flag register */ |
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#define RX_BUSY BIT(0) |
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#define RX_FIFO_EMPTY BIT(1) |
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#define RX_FIFO_FULL BIT(2) |
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#define TX_BUSY BIT(3) |
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#define TX_FIFO_EMPTY BIT(4) |
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#define TX_FIFO_FULL BIT(5) |
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#define RBUSY_SHIFT 0 |
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#define RFE_SHIFT 1 |
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#define RFU_SHIFT 2 |
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#define TBUSY_SHIFT 3 |
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#define TFE_SHIFT 4 |
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#define TFU_SHIFT 5 |
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/* Multichannel control register */ |
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#define RMCEN_SHIFT 0 |
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#define RMCSF_SHIFT 1 |
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#define RCMPM_SHIFT 3 |
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#define TMCEN_SHIFT 5 |
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#define TNCSF_SHIFT 6 |
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/* Sample rate generator register */ |
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#define SCKDIV_SHIFT 0 |
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#define FRWID_SHIFT 10 |
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#define FRPER_SHIFT 16 |
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#define SCK_DIV_MASK 0x0000003FF |
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#define FRAME_WIDTH_BITS(n) (((n) << FRWID_SHIFT) & 0x0000FC00) |
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#define FRAME_PERIOD_BITS(n) (((n) << FRPER_SHIFT) & 0x1FFF0000) |
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/* DMA controller register */ |
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#define RX_DMA_ENABLE BIT(0) |
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#define TX_DMA_ENABLE BIT(1) |
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#define RDMAE_SHIFT 0 |
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#define TDMAE_SHIFT 1 |
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/* Interrupt Register */ |
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#define RX_SERVICE_INT BIT(0) |
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#define RX_OVERRUN_ERROR_INT BIT(1) |
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#define RX_FSYNC_ERR_INT BIT(2) |
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#define RX_FSYNC_INT BIT(3) |
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#define TX_SERVICE_INT BIT(4) |
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#define TX_UNDERRUN_ERR_INT BIT(5) |
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#define TX_FSYNC_ERR_INT BIT(6) |
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#define TX_FSYNC_INT BIT(7) |
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#define ALL_INT 0x000000ff |
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/* MSP test control register */ |
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#define MSP_ITCR_ITEN BIT(0) |
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#define MSP_ITCR_TESTFIFO BIT(1) |
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#define RMCEN_BIT 0 |
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#define RMCSF_BIT 1 |
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#define RCMPM_BIT 3 |
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#define TMCEN_BIT 5 |
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#define TNCSF_BIT 6 |
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/* Single or dual phase mode */ |
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enum msp_phase_mode { |
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MSP_SINGLE_PHASE, |
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MSP_DUAL_PHASE |
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}; |
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/* Frame length */ |
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enum msp_frame_length { |
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MSP_FRAME_LEN_1 = 0, |
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MSP_FRAME_LEN_2 = 1, |
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MSP_FRAME_LEN_4 = 3, |
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MSP_FRAME_LEN_8 = 7, |
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MSP_FRAME_LEN_12 = 11, |
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MSP_FRAME_LEN_16 = 15, |
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MSP_FRAME_LEN_20 = 19, |
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MSP_FRAME_LEN_32 = 31, |
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MSP_FRAME_LEN_48 = 47, |
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MSP_FRAME_LEN_64 = 63 |
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}; |
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/* Element length */ |
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enum msp_elem_length { |
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MSP_ELEM_LEN_8 = 0, |
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MSP_ELEM_LEN_10 = 1, |
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MSP_ELEM_LEN_12 = 2, |
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MSP_ELEM_LEN_14 = 3, |
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MSP_ELEM_LEN_16 = 4, |
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MSP_ELEM_LEN_20 = 5, |
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MSP_ELEM_LEN_24 = 6, |
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MSP_ELEM_LEN_32 = 7 |
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}; |
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enum msp_data_xfer_width { |
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MSP_DATA_TRANSFER_WIDTH_BYTE, |
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MSP_DATA_TRANSFER_WIDTH_HALFWORD, |
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MSP_DATA_TRANSFER_WIDTH_WORD |
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}; |
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enum msp_frame_sync { |
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MSP_FSYNC_UNIGNORE = 0, |
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MSP_FSYNC_IGNORE = 1, |
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}; |
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enum msp_phase2_start_mode { |
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MSP_PHASE2_START_MODE_IMEDIATE, |
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MSP_PHASE2_START_MODE_FSYNC |
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}; |
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enum msp_btf { |
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MSP_BTF_MS_BIT_FIRST = 0, |
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MSP_BTF_LS_BIT_FIRST = 1 |
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}; |
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enum msp_fsync_pol { |
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MSP_FSYNC_POL_ACT_HI = 0, |
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MSP_FSYNC_POL_ACT_LO = 1 |
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}; |
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/* Data delay (in bit clock cycles) */ |
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enum msp_delay { |
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MSP_DELAY_0 = 0, |
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MSP_DELAY_1 = 1, |
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MSP_DELAY_2 = 2, |
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MSP_DELAY_3 = 3 |
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}; |
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/* Configurations of clocks (transmit, receive or sample rate generator) */ |
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enum msp_edge { |
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MSP_FALLING_EDGE = 0, |
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MSP_RISING_EDGE = 1, |
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}; |
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enum msp_hws { |
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MSP_SWAP_NONE = 0, |
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MSP_SWAP_BYTE_PER_WORD = 1, |
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MSP_SWAP_BYTE_PER_HALF_WORD = 2, |
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MSP_SWAP_HALF_WORD_PER_WORD = 3 |
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}; |
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enum msp_compress_mode { |
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MSP_COMPRESS_MODE_LINEAR = 0, |
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MSP_COMPRESS_MODE_MU_LAW = 2, |
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MSP_COMPRESS_MODE_A_LAW = 3 |
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}; |
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enum msp_expand_mode { |
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MSP_EXPAND_MODE_LINEAR = 0, |
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MSP_EXPAND_MODE_LINEAR_SIGNED = 1, |
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MSP_EXPAND_MODE_MU_LAW = 2, |
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MSP_EXPAND_MODE_A_LAW = 3 |
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}; |
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#define MSP_FRAME_PERIOD_IN_MONO_MODE 256 |
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#define MSP_FRAME_PERIOD_IN_STEREO_MODE 32 |
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#define MSP_FRAME_WIDTH_IN_STEREO_MODE 16 |
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enum msp_protocol { |
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MSP_I2S_PROTOCOL, |
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MSP_PCM_PROTOCOL, |
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MSP_PCM_COMPAND_PROTOCOL, |
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MSP_INVALID_PROTOCOL |
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}; |
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/* |
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* No of registers to backup during |
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* suspend resume |
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*/ |
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#define MAX_MSP_BACKUP_REGS 36 |
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enum i2s_direction_t { |
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MSP_DIR_TX = 0x01, |
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MSP_DIR_RX = 0x02, |
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}; |
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enum msp_data_size { |
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MSP_DATA_BITS_DEFAULT = -1, |
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MSP_DATA_BITS_8 = 0x00, |
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MSP_DATA_BITS_10, |
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MSP_DATA_BITS_12, |
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MSP_DATA_BITS_14, |
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MSP_DATA_BITS_16, |
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MSP_DATA_BITS_20, |
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MSP_DATA_BITS_24, |
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MSP_DATA_BITS_32, |
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}; |
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enum msp_state { |
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MSP_STATE_IDLE = 0, |
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MSP_STATE_CONFIGURED = 1, |
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MSP_STATE_RUNNING = 2, |
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}; |
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enum msp_rx_comparison_enable_mode { |
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MSP_COMPARISON_DISABLED = 0, |
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MSP_COMPARISON_NONEQUAL_ENABLED = 2, |
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MSP_COMPARISON_EQUAL_ENABLED = 3 |
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}; |
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struct msp_multichannel_config { |
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bool rx_multichannel_enable; |
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bool tx_multichannel_enable; |
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enum msp_rx_comparison_enable_mode rx_comparison_enable_mode; |
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u8 padding; |
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u32 comparison_value; |
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u32 comparison_mask; |
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u32 rx_channel_0_enable; |
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u32 rx_channel_1_enable; |
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u32 rx_channel_2_enable; |
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u32 rx_channel_3_enable; |
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u32 tx_channel_0_enable; |
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u32 tx_channel_1_enable; |
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u32 tx_channel_2_enable; |
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u32 tx_channel_3_enable; |
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}; |
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struct msp_protdesc { |
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u32 rx_phase_mode; |
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u32 tx_phase_mode; |
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u32 rx_phase2_start_mode; |
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u32 tx_phase2_start_mode; |
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u32 rx_byte_order; |
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u32 tx_byte_order; |
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u32 rx_frame_len_1; |
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u32 rx_frame_len_2; |
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u32 tx_frame_len_1; |
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u32 tx_frame_len_2; |
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u32 rx_elem_len_1; |
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u32 rx_elem_len_2; |
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u32 tx_elem_len_1; |
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u32 tx_elem_len_2; |
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u32 rx_data_delay; |
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u32 tx_data_delay; |
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u32 rx_clk_pol; |
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u32 tx_clk_pol; |
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u32 rx_fsync_pol; |
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u32 tx_fsync_pol; |
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u32 rx_half_word_swap; |
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u32 tx_half_word_swap; |
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u32 compression_mode; |
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u32 expansion_mode; |
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u32 frame_sync_ignore; |
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u32 frame_period; |
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u32 frame_width; |
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u32 clocks_per_frame; |
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}; |
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struct ux500_msp_config { |
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unsigned int f_inputclk; |
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unsigned int rx_clk_sel; |
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unsigned int tx_clk_sel; |
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unsigned int srg_clk_sel; |
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unsigned int rx_fsync_pol; |
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unsigned int tx_fsync_pol; |
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unsigned int rx_fsync_sel; |
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unsigned int tx_fsync_sel; |
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unsigned int rx_fifo_config; |
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unsigned int tx_fifo_config; |
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unsigned int loopback_enable; |
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unsigned int tx_data_enable; |
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unsigned int default_protdesc; |
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struct msp_protdesc protdesc; |
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int multichannel_configured; |
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struct msp_multichannel_config multichannel_config; |
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unsigned int direction; |
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unsigned int protocol; |
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unsigned int frame_freq; |
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enum msp_data_size data_size; |
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unsigned int def_elem_len; |
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unsigned int iodelay; |
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}; |
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struct ux500_msp_dma_params { |
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unsigned int data_size; |
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dma_addr_t tx_rx_addr; |
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struct stedma40_chan_cfg *dma_cfg; |
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}; |
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struct ux500_msp { |
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int id; |
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void __iomem *registers; |
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struct device *dev; |
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struct ux500_msp_dma_params playback_dma_data; |
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struct ux500_msp_dma_params capture_dma_data; |
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enum msp_state msp_state; |
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int def_elem_len; |
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unsigned int dir_busy; |
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int loopback_enable; |
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unsigned int f_bitclk; |
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}; |
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struct msp_i2s_platform_data; |
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int ux500_msp_i2s_init_msp(struct platform_device *pdev, |
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struct ux500_msp **msp_p, |
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struct msp_i2s_platform_data *platform_data); |
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void ux500_msp_i2s_cleanup_msp(struct platform_device *pdev, |
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struct ux500_msp *msp); |
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int ux500_msp_i2s_open(struct ux500_msp *msp, struct ux500_msp_config *config); |
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int ux500_msp_i2s_close(struct ux500_msp *msp, |
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unsigned int dir); |
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int ux500_msp_i2s_trigger(struct ux500_msp *msp, int cmd, |
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int direction); |
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#endif
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