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215 lines
8.2 KiB
215 lines
8.2 KiB
/* SPDX-License-Identifier: GPL-2.0-only */ |
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/* |
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* tegra210_mbdrc.h - Definitions for Tegra210 MBDRC driver |
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* |
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* Copyright (c) 2022, NVIDIA CORPORATION. All rights reserved. |
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* |
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*/ |
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#ifndef __TEGRA210_MBDRC_H__ |
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#define __TEGRA210_MBDRC_H__ |
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#include <linux/platform_device.h> |
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#include <sound/soc.h> |
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/* Register offsets from TEGRA210_MBDRC*_BASE */ |
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#define TEGRA210_MBDRC_SOFT_RESET 0x4 |
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#define TEGRA210_MBDRC_CG 0x8 |
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#define TEGRA210_MBDRC_STATUS 0xc |
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#define TEGRA210_MBDRC_CFG 0x28 |
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#define TEGRA210_MBDRC_CHANNEL_MASK 0x2c |
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#define TEGRA210_MBDRC_MASTER_VOL 0x30 |
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#define TEGRA210_MBDRC_FAST_FACTOR 0x34 |
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#define TEGRA210_MBDRC_FILTER_COUNT 3 |
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#define TEGRA210_MBDRC_FILTER_PARAM_STRIDE 0x4 |
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#define TEGRA210_MBDRC_IIR_CFG 0x38 |
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#define TEGRA210_MBDRC_IN_ATTACK 0x44 |
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#define TEGRA210_MBDRC_IN_RELEASE 0x50 |
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#define TEGRA210_MBDRC_FAST_ATTACK 0x5c |
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#define TEGRA210_MBDRC_IN_THRESHOLD 0x68 |
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#define TEGRA210_MBDRC_OUT_THRESHOLD 0x74 |
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#define TEGRA210_MBDRC_RATIO_1ST 0x80 |
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#define TEGRA210_MBDRC_RATIO_2ND 0x8c |
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#define TEGRA210_MBDRC_RATIO_3RD 0x98 |
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#define TEGRA210_MBDRC_RATIO_4TH 0xa4 |
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#define TEGRA210_MBDRC_RATIO_5TH 0xb0 |
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#define TEGRA210_MBDRC_MAKEUP_GAIN 0xbc |
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#define TEGRA210_MBDRC_INIT_GAIN 0xc8 |
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#define TEGRA210_MBDRC_GAIN_ATTACK 0xd4 |
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#define TEGRA210_MBDRC_GAIN_RELEASE 0xe0 |
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#define TEGRA210_MBDRC_FAST_RELEASE 0xec |
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#define TEGRA210_MBDRC_CFG_RAM_CTRL 0xf8 |
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#define TEGRA210_MBDRC_CFG_RAM_DATA 0x104 |
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#define TEGRA210_MBDRC_MAX_REG (TEGRA210_MBDRC_CFG_RAM_DATA + \ |
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(TEGRA210_MBDRC_FILTER_PARAM_STRIDE * \ |
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(TEGRA210_MBDRC_FILTER_COUNT - 1))) |
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/* Fields for TEGRA210_MBDRC_CFG */ |
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#define TEGRA210_MBDRC_CFG_RMS_OFFSET_SHIFT 16 |
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#define TEGRA210_MBDRC_CFG_RMS_OFFSET_MASK (0x1ff << TEGRA210_MBDRC_CFG_RMS_OFFSET_SHIFT) |
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#define TEGRA210_MBDRC_CFG_PEAK_RMS_SHIFT 14 |
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#define TEGRA210_MBDRC_CFG_PEAK_RMS_MASK (0x1 << TEGRA210_MBDRC_CFG_PEAK_RMS_SHIFT) |
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#define TEGRA210_MBDRC_CFG_PEAK (1 << TEGRA210_MBDRC_CFG_PEAK_RMS_SHIFT) |
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#define TEGRA210_MBDRC_CFG_FILTER_STRUCTURE_SHIFT 13 |
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#define TEGRA210_MBDRC_CFG_FILTER_STRUCTURE_MASK (0x1 << TEGRA210_MBDRC_CFG_FILTER_STRUCTURE_SHIFT) |
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#define TEGRA210_MBDRC_CFG_FILTER_STRUCTURE_FLEX (1 << TEGRA210_MBDRC_CFG_FILTER_STRUCTURE_SHIFT) |
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#define TEGRA210_MBDRC_CFG_SHIFT_CTRL_SHIFT 8 |
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#define TEGRA210_MBDRC_CFG_SHIFT_CTRL_MASK (0x1f << TEGRA210_MBDRC_CFG_SHIFT_CTRL_SHIFT) |
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#define TEGRA210_MBDRC_CFG_FRAME_SIZE_SHIFT 4 |
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#define TEGRA210_MBDRC_CFG_FRAME_SIZE_MASK (0xf << TEGRA210_MBDRC_CFG_FRAME_SIZE_SHIFT) |
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#define TEGRA210_MBDRC_CFG_MBDRC_MODE_SHIFT 0 |
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#define TEGRA210_MBDRC_CFG_MBDRC_MODE_MASK (0x3 << TEGRA210_MBDRC_CFG_MBDRC_MODE_SHIFT) |
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#define TEGRA210_MBDRC_CFG_MBDRC_MODE_BYPASS (0 << TEGRA210_MBDRC_CFG_MBDRC_MODE_SHIFT) |
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/* Fields for TEGRA210_MBDRC_CHANNEL_MASK */ |
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#define TEGRA210_MBDRC_CHANNEL_MASK_SHIFT 0 |
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#define TEGRA210_MBDRC_CHANNEL_MASK_MASK (0xff << TEGRA210_MBDRC_CHANNEL_MASK_SHIFT) |
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/* Fields for TEGRA210_MBDRC_MASTER_VOL */ |
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#define TEGRA210_MBDRC_MASTER_VOL_SHIFT 23 |
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#define TEGRA210_MBDRC_MASTER_VOL_MIN -256 |
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#define TEGRA210_MBDRC_MASTER_VOL_MAX 256 |
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/* Fields for TEGRA210_MBDRC_FAST_FACTOR */ |
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#define TEGRA210_MBDRC_FAST_FACTOR_RELEASE_SHIFT 16 |
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#define TEGRA210_MBDRC_FAST_FACTOR_RELEASE_MASK (0xffff << TEGRA210_MBDRC_FAST_FACTOR_RELEASE_SHIFT) |
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#define TEGRA210_MBDRC_FAST_FACTOR_ATTACK_SHIFT 0 |
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#define TEGRA210_MBDRC_FAST_FACTOR_ATTACK_MASK (0xffff << TEGRA210_MBDRC_FAST_FACTOR_ATTACK_SHIFT) |
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/* Fields for TEGRA210_MBDRC_IIR_CFG */ |
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#define TEGRA210_MBDRC_IIR_CFG_NUM_STAGES_SHIFT 0 |
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#define TEGRA210_MBDRC_IIR_CFG_NUM_STAGES_MASK (0xf << TEGRA210_MBDRC_IIR_CFG_NUM_STAGES_SHIFT) |
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/* Fields for TEGRA210_MBDRC_IN_ATTACK */ |
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#define TEGRA210_MBDRC_IN_ATTACK_TC_SHIFT 0 |
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#define TEGRA210_MBDRC_IN_ATTACK_TC_MASK (0xffffffff << TEGRA210_MBDRC_IN_ATTACK_TC_SHIFT) |
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/* Fields for TEGRA210_MBDRC_IN_RELEASE */ |
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#define TEGRA210_MBDRC_IN_RELEASE_TC_SHIFT 0 |
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#define TEGRA210_MBDRC_IN_RELEASE_TC_MASK (0xffffffff << TEGRA210_MBDRC_IN_RELEASE_TC_SHIFT) |
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/* Fields for TEGRA210_MBDRC_FAST_ATTACK */ |
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#define TEGRA210_MBDRC_FAST_ATTACK_TC_SHIFT 0 |
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#define TEGRA210_MBDRC_FAST_ATTACK_TC_MASK (0xffffffff << TEGRA210_MBDRC_FAST_ATTACK_TC_SHIFT) |
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/* Fields for TEGRA210_MBDRC_IN_THRESHOLD / TEGRA210_MBDRC_OUT_THRESHOLD */ |
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#define TEGRA210_MBDRC_THRESH_4TH_SHIFT 24 |
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#define TEGRA210_MBDRC_THRESH_4TH_MASK (0xff << TEGRA210_MBDRC_THRESH_4TH_SHIFT) |
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#define TEGRA210_MBDRC_THRESH_3RD_SHIFT 16 |
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#define TEGRA210_MBDRC_THRESH_3RD_MASK (0xff << TEGRA210_MBDRC_THRESH_3RD_SHIFT) |
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#define TEGRA210_MBDRC_THRESH_2ND_SHIFT 8 |
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#define TEGRA210_MBDRC_THRESH_2ND_MASK (0xff << TEGRA210_MBDRC_THRESH_2ND_SHIFT) |
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#define TEGRA210_MBDRC_THRESH_1ST_SHIFT 0 |
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#define TEGRA210_MBDRC_THRESH_1ST_MASK (0xff << TEGRA210_MBDRC_THRESH_1ST_SHIFT) |
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/* Fields for TEGRA210_MBDRC_RATIO_1ST */ |
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#define TEGRA210_MBDRC_RATIO_1ST_SHIFT 0 |
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#define TEGRA210_MBDRC_RATIO_1ST_MASK (0xffff << TEGRA210_MBDRC_RATIO_1ST_SHIFT) |
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/* Fields for TEGRA210_MBDRC_RATIO_2ND */ |
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#define TEGRA210_MBDRC_RATIO_2ND_SHIFT 0 |
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#define TEGRA210_MBDRC_RATIO_2ND_MASK (0xffff << TEGRA210_MBDRC_RATIO_2ND_SHIFT) |
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/* Fields for TEGRA210_MBDRC_RATIO_3RD */ |
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#define TEGRA210_MBDRC_RATIO_3RD_SHIFT 0 |
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#define TEGRA210_MBDRC_RATIO_3RD_MASK (0xffff << TEGRA210_MBDRC_RATIO_3RD_SHIFT) |
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/* Fields for TEGRA210_MBDRC_RATIO_4TH */ |
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#define TEGRA210_MBDRC_RATIO_4TH_SHIFT 0 |
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#define TEGRA210_MBDRC_RATIO_4TH_MASK (0xffff << TEGRA210_MBDRC_RATIO_4TH_SHIFT) |
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/* Fields for TEGRA210_MBDRC_RATIO_5TH */ |
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#define TEGRA210_MBDRC_RATIO_5TH_SHIFT 0 |
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#define TEGRA210_MBDRC_RATIO_5TH_MASK (0xffff << TEGRA210_MBDRC_RATIO_5TH_SHIFT) |
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/* Fields for TEGRA210_MBDRC_MAKEUP_GAIN */ |
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#define TEGRA210_MBDRC_MAKEUP_GAIN_SHIFT 0 |
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#define TEGRA210_MBDRC_MAKEUP_GAIN_MASK (0x3f << TEGRA210_MBDRC_MAKEUP_GAIN_SHIFT) |
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/* Fields for TEGRA210_MBDRC_INIT_GAIN */ |
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#define TEGRA210_MBDRC_INIT_GAIN_SHIFT 0 |
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#define TEGRA210_MBDRC_INIT_GAIN_MASK (0xffffffff << TEGRA210_MBDRC_INIT_GAIN_SHIFT) |
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/* Fields for TEGRA210_MBDRC_GAIN_ATTACK */ |
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#define TEGRA210_MBDRC_GAIN_ATTACK_SHIFT 0 |
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#define TEGRA210_MBDRC_GAIN_ATTACK_MASK (0xffffffff << TEGRA210_MBDRC_GAIN_ATTACK_SHIFT) |
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/* Fields for TEGRA210_MBDRC_GAIN_RELEASE */ |
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#define TEGRA210_MBDRC_GAIN_RELEASE_SHIFT 0 |
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#define TEGRA210_MBDRC_GAIN_RELEASE_MASK (0xffffffff << TEGRA210_MBDRC_GAIN_RELEASE_SHIFT) |
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/* Fields for TEGRA210_MBDRC_FAST_RELEASE */ |
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#define TEGRA210_MBDRC_FAST_RELEASE_SHIFT 0 |
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#define TEGRA210_MBDRC_FAST_RELEASE_MASK (0xffffffff << TEGRA210_MBDRC_FAST_RELEASE_SHIFT) |
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#define TEGRA210_MBDRC_RAM_CTRL_RW_READ 0 |
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#define TEGRA210_MBDRC_RAM_CTRL_RW_WRITE (1 << 14) |
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#define TEGRA210_MBDRC_RAM_CTRL_ADDR_INIT_EN (1 << 13) |
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#define TEGRA210_MBDRC_RAM_CTRL_SEQ_ACCESS_EN (1 << 12) |
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#define TEGRA210_MBDRC_RAM_CTRL_RAM_ADDR_MASK 0x1ff |
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/* |
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* Order and size of each structure element for following structures should not |
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* be altered size order of elements and their size are based on PEQ co-eff ram |
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* and shift ram layout. |
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*/ |
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#define TEGRA210_MBDRC_THRESHOLD_NUM 4 |
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#define TEGRA210_MBDRC_RATIO_NUM (TEGRA210_MBDRC_THRESHOLD_NUM + 1) |
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#define TEGRA210_MBDRC_MAX_BIQUAD_STAGES 8 |
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/* Order of these enums are same as the order of band specific hw registers */ |
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enum { |
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MBDRC_LOW_BAND, |
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MBDRC_MID_BAND, |
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MBDRC_HIGH_BAND, |
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MBDRC_NUM_BAND, |
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}; |
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struct tegra210_mbdrc_band_params { |
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u32 band; |
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u32 iir_stages; |
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u32 in_attack_tc; |
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u32 in_release_tc; |
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u32 fast_attack_tc; |
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u32 in_threshold[TEGRA210_MBDRC_THRESHOLD_NUM]; |
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u32 out_threshold[TEGRA210_MBDRC_THRESHOLD_NUM]; |
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u32 ratio[TEGRA210_MBDRC_RATIO_NUM]; |
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u32 makeup_gain; |
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u32 gain_init; |
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u32 gain_attack_tc; |
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u32 gain_release_tc; |
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u32 fast_release_tc; |
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/* For biquad_params[][5] order of coeff is b0, b1, a0, a1, a2 */ |
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u32 biquad_params[TEGRA210_MBDRC_MAX_BIQUAD_STAGES * 5]; |
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}; |
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struct tegra210_mbdrc_config { |
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unsigned int mode; |
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unsigned int rms_off; |
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unsigned int peak_rms_mode; |
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unsigned int fliter_structure; |
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unsigned int shift_ctrl; |
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unsigned int frame_size; |
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unsigned int channel_mask; |
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unsigned int fa_factor; /* Fast attack factor */ |
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unsigned int fr_factor; /* Fast release factor */ |
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struct tegra210_mbdrc_band_params band_params[MBDRC_NUM_BAND]; |
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}; |
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int tegra210_mbdrc_regmap_init(struct platform_device *pdev); |
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int tegra210_mbdrc_component_init(struct snd_soc_component *cmpnt); |
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int tegra210_mbdrc_hw_params(struct snd_soc_component *cmpnt); |
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#endif
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