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238 lines
3.6 KiB
238 lines
3.6 KiB
// SPDX-License-Identifier: GPL-2.0+ |
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/* |
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* (C) Copyright 2002 |
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* Wolfgang Denk, DENX Software Engineering, [email protected]. |
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*/ |
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#include <common.h> |
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/* |
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* CPU test |
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* Ternary instructions instr rD,rA,rB |
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* |
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* Arithmetic instructions: add, addc, adde, subf, subfc, subfe, |
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* mullw, mulhw, mulhwu, divw, divwu |
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* |
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* The test contains a pre-built table of instructions, operands and |
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* expected results. For each table entry, the test will cyclically use |
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* different sets of operand registers and result registers. |
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*/ |
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#include <post.h> |
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#include "cpu_asm.h" |
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#if CONFIG_POST & CONFIG_SYS_POST_CPU |
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extern void cpu_post_exec_22 (ulong *code, ulong *cr, ulong *res, ulong op1, |
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ulong op2); |
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extern ulong cpu_post_makecr (long v); |
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static struct cpu_post_three_s |
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{ |
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ulong cmd; |
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ulong op1; |
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ulong op2; |
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ulong res; |
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} cpu_post_three_table[] = |
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{ |
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{ |
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OP_ADD, |
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100, |
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200, |
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300 |
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}, |
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{ |
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OP_ADD, |
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100, |
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-200, |
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-100 |
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}, |
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{ |
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OP_ADDC, |
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100, |
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200, |
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300 |
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}, |
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{ |
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OP_ADDC, |
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100, |
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-200, |
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-100 |
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}, |
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{ |
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OP_ADDE, |
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100, |
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200, |
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300 |
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}, |
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{ |
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OP_ADDE, |
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100, |
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-200, |
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-100 |
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}, |
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{ |
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OP_SUBF, |
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100, |
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200, |
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100 |
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}, |
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{ |
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OP_SUBF, |
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300, |
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200, |
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-100 |
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}, |
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{ |
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OP_SUBFC, |
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100, |
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200, |
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100 |
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}, |
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{ |
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OP_SUBFC, |
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300, |
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200, |
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-100 |
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}, |
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{ |
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OP_SUBFE, |
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100, |
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200, |
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200 + ~100 |
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}, |
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{ |
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OP_SUBFE, |
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300, |
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200, |
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200 + ~300 |
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}, |
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{ |
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OP_MULLW, |
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200, |
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300, |
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200 * 300 |
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}, |
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{ |
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OP_MULHW, |
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0x10000000, |
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0x10000000, |
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0x1000000 |
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}, |
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{ |
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OP_MULHWU, |
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0x80000000, |
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0x80000000, |
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0x40000000 |
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}, |
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{ |
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OP_DIVW, |
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-20, |
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5, |
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-4 |
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}, |
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{ |
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OP_DIVWU, |
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0x8000, |
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0x200, |
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0x40 |
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}, |
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}; |
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static unsigned int cpu_post_three_size = ARRAY_SIZE(cpu_post_three_table); |
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int cpu_post_test_three (void) |
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{ |
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int ret = 0; |
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unsigned int i, reg; |
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int flag = disable_interrupts(); |
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for (i = 0; i < cpu_post_three_size && ret == 0; i++) |
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{ |
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struct cpu_post_three_s *test = cpu_post_three_table + i; |
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for (reg = 0; reg < 32 && ret == 0; reg++) |
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{ |
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unsigned int reg0 = (reg + 0) % 32; |
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unsigned int reg1 = (reg + 1) % 32; |
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unsigned int reg2 = (reg + 2) % 32; |
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unsigned int stk = reg < 16 ? 31 : 15; |
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unsigned long code[] = |
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{ |
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ASM_STW(stk, 1, -4), |
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ASM_ADDI(stk, 1, -24), |
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ASM_STW(3, stk, 12), |
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ASM_STW(4, stk, 16), |
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ASM_STW(reg0, stk, 8), |
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ASM_STW(reg1, stk, 4), |
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ASM_STW(reg2, stk, 0), |
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ASM_LWZ(reg1, stk, 12), |
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ASM_LWZ(reg0, stk, 16), |
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ASM_12(test->cmd, reg2, reg1, reg0), |
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ASM_STW(reg2, stk, 12), |
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ASM_LWZ(reg2, stk, 0), |
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ASM_LWZ(reg1, stk, 4), |
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ASM_LWZ(reg0, stk, 8), |
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ASM_LWZ(3, stk, 12), |
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ASM_ADDI(1, stk, 24), |
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ASM_LWZ(stk, 1, -4), |
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ASM_BLR, |
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}; |
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unsigned long codecr[] = |
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{ |
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ASM_STW(stk, 1, -4), |
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ASM_ADDI(stk, 1, -24), |
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ASM_STW(3, stk, 12), |
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ASM_STW(4, stk, 16), |
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ASM_STW(reg0, stk, 8), |
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ASM_STW(reg1, stk, 4), |
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ASM_STW(reg2, stk, 0), |
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ASM_LWZ(reg1, stk, 12), |
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ASM_LWZ(reg0, stk, 16), |
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ASM_12(test->cmd, reg2, reg1, reg0) | BIT_C, |
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ASM_STW(reg2, stk, 12), |
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ASM_LWZ(reg2, stk, 0), |
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ASM_LWZ(reg1, stk, 4), |
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ASM_LWZ(reg0, stk, 8), |
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ASM_LWZ(3, stk, 12), |
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ASM_ADDI(1, stk, 24), |
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ASM_LWZ(stk, 1, -4), |
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ASM_BLR, |
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}; |
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ulong res; |
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ulong cr; |
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if (ret == 0) |
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{ |
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cr = 0; |
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cpu_post_exec_22 (code, & cr, & res, test->op1, test->op2); |
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ret = res == test->res && cr == 0 ? 0 : -1; |
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if (ret != 0) |
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{ |
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post_log ("Error at three test %d !\n", i); |
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} |
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} |
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if (ret == 0) |
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{ |
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cpu_post_exec_22 (codecr, & cr, & res, test->op1, test->op2); |
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ret = res == test->res && |
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(cr & 0xe0000000) == cpu_post_makecr (res) ? 0 : -1; |
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if (ret != 0) |
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{ |
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post_log ("Error at three test %d !\n", i); |
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} |
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} |
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} |
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} |
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if (flag) |
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enable_interrupts(); |
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return ret; |
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} |
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#endif
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