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341 lines
7.8 KiB
341 lines
7.8 KiB
// SPDX-License-Identifier: GPL-2.0+ |
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/* |
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* Copyright (C) 2011 Marek Vasut <[email protected]> |
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* |
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* (C) Copyright 2002 |
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* Wolfgang Denk, DENX Software Engineering, <[email protected]> |
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* |
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* (C) Copyright 2002 |
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* Sysgo Real-Time Solutions, GmbH <www.elinos.com> |
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* Marius Groeger <[email protected]> |
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* |
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* (C) Copyright 2002 |
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* Sysgo Real-Time Solutions, GmbH <www.elinos.com> |
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* Alex Zuepke <[email protected]> |
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* |
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* Copyright (C) 1999 2000 2001 Erik Mouw ([email protected]) |
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* |
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* Modified to add driver model (DM) support |
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* (C) Copyright 2016 Marcel Ziswiler <[email protected]> |
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*/ |
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#include <common.h> |
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#include <asm/arch/pxa-regs.h> |
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#include <asm/arch/regs-uart.h> |
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#include <asm/io.h> |
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#include <dm.h> |
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#include <dm/platform_data/serial_pxa.h> |
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#include <linux/compiler.h> |
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#include <serial.h> |
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#include <watchdog.h> |
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DECLARE_GLOBAL_DATA_PTR; |
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static uint32_t pxa_uart_get_baud_divider(int baudrate) |
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{ |
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return 921600 / baudrate; |
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} |
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static void pxa_uart_toggle_clock(uint32_t uart_index, int enable) |
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{ |
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uint32_t clk_reg, clk_offset, reg; |
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clk_reg = UART_CLK_REG; |
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clk_offset = UART_CLK_BASE << uart_index; |
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reg = readl(clk_reg); |
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if (enable) |
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reg |= clk_offset; |
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else |
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reg &= ~clk_offset; |
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writel(reg, clk_reg); |
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} |
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/* |
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* Enable clock and set baud rate, parity etc. |
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*/ |
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void pxa_setbrg_common(struct pxa_uart_regs *uart_regs, int port, int baudrate) |
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{ |
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uint32_t divider = pxa_uart_get_baud_divider(baudrate); |
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if (!divider) |
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hang(); |
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pxa_uart_toggle_clock(port, 1); |
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/* Disable interrupts and FIFOs */ |
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writel(0, &uart_regs->ier); |
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writel(0, &uart_regs->fcr); |
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/* Set baud rate */ |
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writel(LCR_WLS0 | LCR_WLS1 | LCR_DLAB, &uart_regs->lcr); |
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writel(divider & 0xff, &uart_regs->dll); |
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writel(divider >> 8, &uart_regs->dlh); |
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writel(LCR_WLS0 | LCR_WLS1, &uart_regs->lcr); |
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/* Enable UART */ |
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writel(IER_UUE, &uart_regs->ier); |
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} |
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#ifndef CONFIG_DM_SERIAL |
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static struct pxa_uart_regs *pxa_uart_index_to_regs(uint32_t uart_index) |
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{ |
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switch (uart_index) { |
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case FFUART_INDEX: return (struct pxa_uart_regs *)FFUART_BASE; |
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case BTUART_INDEX: return (struct pxa_uart_regs *)BTUART_BASE; |
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case STUART_INDEX: return (struct pxa_uart_regs *)STUART_BASE; |
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case HWUART_INDEX: return (struct pxa_uart_regs *)HWUART_BASE; |
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default: |
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return NULL; |
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} |
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} |
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/* |
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* Enable clock and set baud rate, parity etc. |
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*/ |
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void pxa_setbrg_dev(uint32_t uart_index) |
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{ |
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struct pxa_uart_regs *uart_regs = pxa_uart_index_to_regs(uart_index); |
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if (!uart_regs) |
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panic("Failed getting UART registers\n"); |
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pxa_setbrg_common(uart_regs, uart_index, gd->baudrate); |
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} |
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/* |
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* Initialise the serial port with the given baudrate. The settings |
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* are always 8 data bits, no parity, 1 stop bit, no start bits. |
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*/ |
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int pxa_init_dev(unsigned int uart_index) |
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{ |
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pxa_setbrg_dev(uart_index); |
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return 0; |
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} |
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/* |
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* Output a single byte to the serial port. |
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*/ |
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void pxa_putc_dev(unsigned int uart_index, const char c) |
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{ |
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struct pxa_uart_regs *uart_regs; |
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/* If \n, also do \r */ |
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if (c == '\n') |
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pxa_putc_dev(uart_index, '\r'); |
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uart_regs = pxa_uart_index_to_regs(uart_index); |
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if (!uart_regs) |
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hang(); |
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while (!(readl(&uart_regs->lsr) & LSR_TEMT)) |
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WATCHDOG_RESET(); |
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writel(c, &uart_regs->thr); |
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} |
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/* |
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* Read a single byte from the serial port. Returns 1 on success, 0 |
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* otherwise. When the function is succesfull, the character read is |
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* written into its argument c. |
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*/ |
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int pxa_tstc_dev(unsigned int uart_index) |
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{ |
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struct pxa_uart_regs *uart_regs; |
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uart_regs = pxa_uart_index_to_regs(uart_index); |
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if (!uart_regs) |
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return -1; |
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return readl(&uart_regs->lsr) & LSR_DR; |
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} |
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/* |
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* Read a single byte from the serial port. Returns 1 on success, 0 |
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* otherwise. When the function is succesfull, the character read is |
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* written into its argument c. |
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*/ |
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int pxa_getc_dev(unsigned int uart_index) |
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{ |
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struct pxa_uart_regs *uart_regs; |
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uart_regs = pxa_uart_index_to_regs(uart_index); |
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if (!uart_regs) |
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return -1; |
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while (!(readl(&uart_regs->lsr) & LSR_DR)) |
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WATCHDOG_RESET(); |
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return readl(&uart_regs->rbr) & 0xff; |
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} |
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void pxa_puts_dev(unsigned int uart_index, const char *s) |
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{ |
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while (*s) |
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pxa_putc_dev(uart_index, *s++); |
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} |
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#define pxa_uart(uart, UART) \ |
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int uart##_init(void) \ |
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{ \ |
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return pxa_init_dev(UART##_INDEX); \ |
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} \ |
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\ |
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void uart##_setbrg(void) \ |
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{ \ |
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return pxa_setbrg_dev(UART##_INDEX); \ |
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} \ |
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\ |
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void uart##_putc(const char c) \ |
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{ \ |
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return pxa_putc_dev(UART##_INDEX, c); \ |
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} \ |
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\ |
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void uart##_puts(const char *s) \ |
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{ \ |
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return pxa_puts_dev(UART##_INDEX, s); \ |
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} \ |
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\ |
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int uart##_getc(void) \ |
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{ \ |
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return pxa_getc_dev(UART##_INDEX); \ |
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} \ |
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\ |
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int uart##_tstc(void) \ |
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{ \ |
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return pxa_tstc_dev(UART##_INDEX); \ |
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} \ |
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#define pxa_uart_desc(uart) \ |
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struct serial_device serial_##uart##_device = \ |
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{ \ |
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.name = "serial_"#uart, \ |
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.start = uart##_init, \ |
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.stop = NULL, \ |
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.setbrg = uart##_setbrg, \ |
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.getc = uart##_getc, \ |
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.tstc = uart##_tstc, \ |
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.putc = uart##_putc, \ |
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.puts = uart##_puts, \ |
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}; |
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#define pxa_uart_multi(uart, UART) \ |
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pxa_uart(uart, UART) \ |
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pxa_uart_desc(uart) |
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#if defined(CONFIG_HWUART) |
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pxa_uart_multi(hwuart, HWUART) |
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#endif |
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#if defined(CONFIG_STUART) |
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pxa_uart_multi(stuart, STUART) |
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#endif |
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#if defined(CONFIG_FFUART) |
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pxa_uart_multi(ffuart, FFUART) |
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#endif |
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#if defined(CONFIG_BTUART) |
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pxa_uart_multi(btuart, BTUART) |
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#endif |
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__weak struct serial_device *default_serial_console(void) |
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{ |
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#if CONFIG_CONS_INDEX == 1 |
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return &serial_hwuart_device; |
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#elif CONFIG_CONS_INDEX == 2 |
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return &serial_stuart_device; |
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#elif CONFIG_CONS_INDEX == 3 |
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return &serial_ffuart_device; |
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#elif CONFIG_CONS_INDEX == 4 |
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return &serial_btuart_device; |
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#else |
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#error "Bad CONFIG_CONS_INDEX." |
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#endif |
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} |
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void pxa_serial_initialize(void) |
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{ |
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#if defined(CONFIG_FFUART) |
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serial_register(&serial_ffuart_device); |
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#endif |
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#if defined(CONFIG_BTUART) |
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serial_register(&serial_btuart_device); |
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#endif |
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#if defined(CONFIG_STUART) |
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serial_register(&serial_stuart_device); |
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#endif |
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} |
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#endif /* CONFIG_DM_SERIAL */ |
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#ifdef CONFIG_DM_SERIAL |
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static int pxa_serial_probe(struct udevice *dev) |
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{ |
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struct pxa_serial_platdata *plat = dev->platdata; |
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pxa_setbrg_common((struct pxa_uart_regs *)plat->base, plat->port, |
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plat->baudrate); |
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return 0; |
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} |
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static int pxa_serial_putc(struct udevice *dev, const char ch) |
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{ |
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struct pxa_serial_platdata *plat = dev->platdata; |
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struct pxa_uart_regs *uart_regs = (struct pxa_uart_regs *)plat->base; |
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/* Wait for last character to go. */ |
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if (!(readl(&uart_regs->lsr) & LSR_TEMT)) |
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return -EAGAIN; |
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writel(ch, &uart_regs->thr); |
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return 0; |
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} |
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static int pxa_serial_getc(struct udevice *dev) |
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{ |
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struct pxa_serial_platdata *plat = dev->platdata; |
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struct pxa_uart_regs *uart_regs = (struct pxa_uart_regs *)plat->base; |
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/* Wait for a character to arrive. */ |
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if (!(readl(&uart_regs->lsr) & LSR_DR)) |
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return -EAGAIN; |
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return readl(&uart_regs->rbr) & 0xff; |
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} |
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int pxa_serial_setbrg(struct udevice *dev, int baudrate) |
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{ |
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struct pxa_serial_platdata *plat = dev->platdata; |
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struct pxa_uart_regs *uart_regs = (struct pxa_uart_regs *)plat->base; |
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int port = plat->port; |
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pxa_setbrg_common(uart_regs, port, baudrate); |
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return 0; |
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} |
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static int pxa_serial_pending(struct udevice *dev, bool input) |
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{ |
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struct pxa_serial_platdata *plat = dev->platdata; |
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struct pxa_uart_regs *uart_regs = (struct pxa_uart_regs *)plat->base; |
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if (input) |
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return readl(&uart_regs->lsr) & LSR_DR ? 1 : 0; |
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else |
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return readl(&uart_regs->lsr) & LSR_TEMT ? 0 : 1; |
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return 0; |
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} |
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static const struct dm_serial_ops pxa_serial_ops = { |
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.putc = pxa_serial_putc, |
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.pending = pxa_serial_pending, |
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.getc = pxa_serial_getc, |
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.setbrg = pxa_serial_setbrg, |
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}; |
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U_BOOT_DRIVER(serial_pxa) = { |
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.name = "serial_pxa", |
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.id = UCLASS_SERIAL, |
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.probe = pxa_serial_probe, |
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.ops = &pxa_serial_ops, |
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.flags = DM_FLAG_PRE_RELOC, |
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}; |
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#endif /* CONFIG_DM_SERIAL */
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