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297 lines
8.1 KiB
297 lines
8.1 KiB
// SPDX-License-Identifier: GPL-2.0+ |
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/* |
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* Copyright (C) 2017 Álvaro Fernández Rojas <[email protected]> |
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* |
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* Derived from linux/drivers/tty/serial/bcm63xx_uart.c: |
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* Copyright (C) 2008 Maxime Bizon <[email protected]> |
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*/ |
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#include <clk.h> |
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#include <dm.h> |
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#include <debug_uart.h> |
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#include <errno.h> |
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#include <serial.h> |
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#include <asm/io.h> |
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#include <asm/types.h> |
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/* UART Control register */ |
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#define UART_CTL_REG 0x0 |
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#define UART_CTL_RXTIMEOUT_MASK 0x1f |
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#define UART_CTL_RXTIMEOUT_5 0x5 |
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#define UART_CTL_RSTRXFIFO_SHIFT 6 |
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#define UART_CTL_RSTRXFIFO_MASK (1 << UART_CTL_RSTRXFIFO_SHIFT) |
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#define UART_CTL_RSTTXFIFO_SHIFT 7 |
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#define UART_CTL_RSTTXFIFO_MASK (1 << UART_CTL_RSTTXFIFO_SHIFT) |
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#define UART_CTL_STOPBITS_SHIFT 8 |
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#define UART_CTL_STOPBITS_MASK (0xf << UART_CTL_STOPBITS_SHIFT) |
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#define UART_CTL_STOPBITS_1 (0x7 << UART_CTL_STOPBITS_SHIFT) |
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#define UART_CTL_BITSPERSYM_SHIFT 12 |
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#define UART_CTL_BITSPERSYM_MASK (0x3 << UART_CTL_BITSPERSYM_SHIFT) |
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#define UART_CTL_BITSPERSYM_8 (0x3 << UART_CTL_BITSPERSYM_SHIFT) |
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#define UART_CTL_XMITBRK_SHIFT 14 |
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#define UART_CTL_XMITBRK_MASK (1 << UART_CTL_XMITBRK_SHIFT) |
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#define UART_CTL_RSVD_SHIFT 15 |
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#define UART_CTL_RSVD_MASK (1 << UART_CTL_RSVD_SHIFT) |
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#define UART_CTL_RXPAREVEN_SHIFT 16 |
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#define UART_CTL_RXPAREVEN_MASK (1 << UART_CTL_RXPAREVEN_SHIFT) |
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#define UART_CTL_RXPAREN_SHIFT 17 |
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#define UART_CTL_RXPAREN_MASK (1 << UART_CTL_RXPAREN_SHIFT) |
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#define UART_CTL_TXPAREVEN_SHIFT 18 |
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#define UART_CTL_TXPAREVEN_MASK (1 << UART_CTL_TXPAREVEN_SHIFT) |
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#define UART_CTL_TXPAREN_SHIFT 19 |
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#define UART_CTL_TXPAREN_MASK (1 << UART_CTL_TXPAREN_SHIFT) |
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#define UART_CTL_LOOPBACK_SHIFT 20 |
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#define UART_CTL_LOOPBACK_MASK (1 << UART_CTL_LOOPBACK_SHIFT) |
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#define UART_CTL_RXEN_SHIFT 21 |
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#define UART_CTL_RXEN_MASK (1 << UART_CTL_RXEN_SHIFT) |
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#define UART_CTL_TXEN_SHIFT 22 |
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#define UART_CTL_TXEN_MASK (1 << UART_CTL_TXEN_SHIFT) |
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#define UART_CTL_BRGEN_SHIFT 23 |
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#define UART_CTL_BRGEN_MASK (1 << UART_CTL_BRGEN_SHIFT) |
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/* UART Baudword register */ |
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#define UART_BAUD_REG 0x4 |
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/* UART FIFO Config register */ |
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#define UART_FIFO_CFG_REG 0x8 |
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#define UART_FIFO_CFG_RX_SHIFT 8 |
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#define UART_FIFO_CFG_RX_MASK (0xf << UART_FIFO_CFG_RX_SHIFT) |
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#define UART_FIFO_CFG_RX_4 (0x4 << UART_FIFO_CFG_RX_SHIFT) |
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#define UART_FIFO_CFG_TX_SHIFT 12 |
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#define UART_FIFO_CFG_TX_MASK (0xf << UART_FIFO_CFG_TX_SHIFT) |
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#define UART_FIFO_CFG_TX_4 (0x4 << UART_FIFO_CFG_TX_SHIFT) |
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/* UART Interrupt register */ |
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#define UART_IR_REG 0x10 |
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#define UART_IR_STAT(x) (1 << (x)) |
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#define UART_IR_TXEMPTY 5 |
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#define UART_IR_RXOVER 7 |
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#define UART_IR_RXNOTEMPTY 11 |
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/* UART FIFO register */ |
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#define UART_FIFO_REG 0x14 |
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#define UART_FIFO_VALID_MASK 0xff |
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#define UART_FIFO_FRAMEERR_SHIFT 8 |
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#define UART_FIFO_FRAMEERR_MASK (1 << UART_FIFO_FRAMEERR_SHIFT) |
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#define UART_FIFO_PARERR_SHIFT 9 |
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#define UART_FIFO_PARERR_MASK (1 << UART_FIFO_PARERR_SHIFT) |
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#define UART_FIFO_BRKDET_SHIFT 10 |
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#define UART_FIFO_BRKDET_MASK (1 << UART_FIFO_BRKDET_SHIFT) |
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#define UART_FIFO_ANYERR_MASK (UART_FIFO_FRAMEERR_MASK | \ |
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UART_FIFO_PARERR_MASK | \ |
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UART_FIFO_BRKDET_MASK) |
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struct bcm6345_serial_priv { |
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void __iomem *base; |
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ulong uartclk; |
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}; |
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/* enable rx & tx operation on uart */ |
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static void bcm6345_serial_enable(void __iomem *base) |
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{ |
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setbits_be32(base + UART_CTL_REG, UART_CTL_BRGEN_MASK | |
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UART_CTL_TXEN_MASK | UART_CTL_RXEN_MASK); |
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} |
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/* disable rx & tx operation on uart */ |
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static void bcm6345_serial_disable(void __iomem *base) |
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{ |
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clrbits_be32(base + UART_CTL_REG, UART_CTL_BRGEN_MASK | |
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UART_CTL_TXEN_MASK | UART_CTL_RXEN_MASK); |
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} |
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/* clear all unread data in rx fifo and unsent data in tx fifo */ |
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static void bcm6345_serial_flush(void __iomem *base) |
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{ |
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/* empty rx and tx fifo */ |
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setbits_be32(base + UART_CTL_REG, UART_CTL_RSTRXFIFO_MASK | |
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UART_CTL_RSTTXFIFO_MASK); |
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/* read any pending char to make sure all irq status are cleared */ |
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readl_be(base + UART_FIFO_REG); |
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} |
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static int bcm6345_serial_init(void __iomem *base, ulong clk, u32 baudrate) |
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{ |
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u32 val; |
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/* mask all irq and flush port */ |
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bcm6345_serial_disable(base); |
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bcm6345_serial_flush(base); |
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/* set uart control config */ |
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clrsetbits_be32(base + UART_CTL_REG, |
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/* clear rx timeout */ |
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UART_CTL_RXTIMEOUT_MASK | |
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/* clear stop bits */ |
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UART_CTL_STOPBITS_MASK | |
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/* clear bits per symbol */ |
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UART_CTL_BITSPERSYM_MASK | |
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/* clear xmit break */ |
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UART_CTL_XMITBRK_MASK | |
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/* clear reserved bit */ |
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UART_CTL_RSVD_MASK | |
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/* disable parity */ |
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UART_CTL_RXPAREN_MASK | |
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UART_CTL_TXPAREN_MASK | |
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/* disable loopback */ |
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UART_CTL_LOOPBACK_MASK, |
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/* set timeout to 5 */ |
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UART_CTL_RXTIMEOUT_5 | |
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/* set 8 bits/symbol */ |
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UART_CTL_BITSPERSYM_8 | |
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/* set 1 stop bit */ |
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UART_CTL_STOPBITS_1 | |
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/* set parity to even */ |
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UART_CTL_RXPAREVEN_MASK | |
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UART_CTL_TXPAREVEN_MASK); |
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/* set uart fifo config */ |
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clrsetbits_be32(base + UART_FIFO_CFG_REG, |
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/* clear fifo config */ |
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UART_FIFO_CFG_RX_MASK | |
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UART_FIFO_CFG_TX_MASK, |
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/* set fifo config to 4 */ |
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UART_FIFO_CFG_RX_4 | |
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UART_FIFO_CFG_TX_4); |
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/* set baud rate */ |
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val = ((clk / baudrate) >> 4); |
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if (val & 0x1) |
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val = (val >> 1); |
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else |
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val = (val >> 1) - 1; |
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writel_be(val, base + UART_BAUD_REG); |
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/* clear interrupts */ |
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writel_be(0, base + UART_IR_REG); |
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/* enable uart */ |
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bcm6345_serial_enable(base); |
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return 0; |
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} |
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static int bcm6345_serial_pending(struct udevice *dev, bool input) |
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{ |
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struct bcm6345_serial_priv *priv = dev_get_priv(dev); |
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u32 val = readl_be(priv->base + UART_IR_REG); |
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if (input) |
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return !!(val & UART_IR_STAT(UART_IR_RXNOTEMPTY)); |
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else |
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return !(val & UART_IR_STAT(UART_IR_TXEMPTY)); |
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} |
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static int bcm6345_serial_setbrg(struct udevice *dev, int baudrate) |
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{ |
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struct bcm6345_serial_priv *priv = dev_get_priv(dev); |
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return bcm6345_serial_init(priv->base, priv->uartclk, baudrate); |
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} |
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static int bcm6345_serial_putc(struct udevice *dev, const char ch) |
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{ |
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struct bcm6345_serial_priv *priv = dev_get_priv(dev); |
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u32 val; |
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val = readl_be(priv->base + UART_IR_REG); |
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if (!(val & UART_IR_STAT(UART_IR_TXEMPTY))) |
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return -EAGAIN; |
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writel_be(ch, priv->base + UART_FIFO_REG); |
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return 0; |
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} |
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static int bcm6345_serial_getc(struct udevice *dev) |
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{ |
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struct bcm6345_serial_priv *priv = dev_get_priv(dev); |
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u32 val; |
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val = readl_be(priv->base + UART_IR_REG); |
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if (val & UART_IR_STAT(UART_IR_RXOVER)) |
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setbits_be32(priv->base + UART_CTL_REG, |
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UART_CTL_RSTRXFIFO_MASK); |
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if (!(val & UART_IR_STAT(UART_IR_RXNOTEMPTY))) |
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return -EAGAIN; |
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val = readl_be(priv->base + UART_FIFO_REG); |
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if (val & UART_FIFO_ANYERR_MASK) |
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return -EAGAIN; |
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return val & UART_FIFO_VALID_MASK; |
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} |
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static int bcm6345_serial_probe(struct udevice *dev) |
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{ |
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struct bcm6345_serial_priv *priv = dev_get_priv(dev); |
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struct clk clk; |
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int ret; |
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/* get address */ |
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priv->base = dev_remap_addr(dev); |
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if (!priv->base) |
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return -EINVAL; |
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/* get clock rate */ |
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ret = clk_get_by_index(dev, 0, &clk); |
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if (ret < 0) |
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return ret; |
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priv->uartclk = clk_get_rate(&clk); |
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clk_free(&clk); |
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/* initialize serial */ |
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return bcm6345_serial_init(priv->base, priv->uartclk, CONFIG_BAUDRATE); |
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} |
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static const struct dm_serial_ops bcm6345_serial_ops = { |
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.putc = bcm6345_serial_putc, |
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.pending = bcm6345_serial_pending, |
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.getc = bcm6345_serial_getc, |
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.setbrg = bcm6345_serial_setbrg, |
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}; |
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static const struct udevice_id bcm6345_serial_ids[] = { |
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{ .compatible = "brcm,bcm6345-uart" }, |
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{ /* sentinel */ } |
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}; |
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U_BOOT_DRIVER(bcm6345_serial) = { |
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.name = "bcm6345-uart", |
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.id = UCLASS_SERIAL, |
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.of_match = bcm6345_serial_ids, |
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.probe = bcm6345_serial_probe, |
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.priv_auto_alloc_size = sizeof(struct bcm6345_serial_priv), |
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.ops = &bcm6345_serial_ops, |
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.flags = DM_FLAG_PRE_RELOC, |
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}; |
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#ifdef CONFIG_DEBUG_UART_BCM6345 |
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static inline void _debug_uart_init(void) |
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{ |
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void __iomem *base = (void __iomem *)CONFIG_DEBUG_UART_BASE; |
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bcm6345_serial_init(base, CONFIG_DEBUG_UART_CLOCK, CONFIG_BAUDRATE); |
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} |
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static inline void wait_xfered(void __iomem *base) |
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{ |
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do { |
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u32 val = readl_be(base + UART_IR_REG); |
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if (val & UART_IR_STAT(UART_IR_TXEMPTY)) |
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break; |
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} while (1); |
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} |
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static inline void _debug_uart_putc(int ch) |
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{ |
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void __iomem *base = (void __iomem *)CONFIG_DEBUG_UART_BASE; |
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wait_xfered(base); |
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writel_be(ch, base + UART_FIFO_REG); |
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wait_xfered(base); |
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} |
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DEBUG_UART_FUNCS |
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#endif
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