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408 lines
11 KiB
408 lines
11 KiB
// SPDX-License-Identifier: GPL-2.0+ |
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/* |
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* Copyright (C) 2017, STMicroelectronics - All Rights Reserved |
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* Author(s): Vikas Manocha, <[email protected]> for STMicroelectronics. |
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*/ |
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#include <common.h> |
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#include <clk.h> |
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#include <dm.h> |
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#include <ram.h> |
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#include <asm/io.h> |
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#define MEM_MODE_MASK GENMASK(2, 0) |
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#define SWP_FMC_OFFSET 10 |
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#define SWP_FMC_MASK GENMASK(SWP_FMC_OFFSET+1, SWP_FMC_OFFSET) |
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#define NOT_FOUND 0xff |
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struct stm32_fmc_regs { |
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/* 0x0 */ |
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u32 bcr1; /* NOR/PSRAM Chip select control register 1 */ |
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u32 btr1; /* SRAM/NOR-Flash Chip select timing register 1 */ |
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u32 bcr2; /* NOR/PSRAM Chip select Control register 2 */ |
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u32 btr2; /* SRAM/NOR-Flash Chip select timing register 2 */ |
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u32 bcr3; /* NOR/PSRAMChip select Control register 3 */ |
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u32 btr3; /* SRAM/NOR-Flash Chip select timing register 3 */ |
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u32 bcr4; /* NOR/PSRAM Chip select Control register 4 */ |
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u32 btr4; /* SRAM/NOR-Flash Chip select timing register 4 */ |
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u32 reserved1[24]; |
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/* 0x80 */ |
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u32 pcr; /* NAND Flash control register */ |
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u32 sr; /* FIFO status and interrupt register */ |
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u32 pmem; /* Common memory space timing register */ |
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u32 patt; /* Attribute memory space timing registers */ |
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u32 reserved2[1]; |
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u32 eccr; /* ECC result registers */ |
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u32 reserved3[27]; |
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/* 0x104 */ |
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u32 bwtr1; /* SRAM/NOR-Flash write timing register 1 */ |
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u32 reserved4[1]; |
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u32 bwtr2; /* SRAM/NOR-Flash write timing register 2 */ |
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u32 reserved5[1]; |
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u32 bwtr3; /* SRAM/NOR-Flash write timing register 3 */ |
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u32 reserved6[1]; |
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u32 bwtr4; /* SRAM/NOR-Flash write timing register 4 */ |
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u32 reserved7[8]; |
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/* 0x140 */ |
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u32 sdcr1; /* SDRAM Control register 1 */ |
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u32 sdcr2; /* SDRAM Control register 2 */ |
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u32 sdtr1; /* SDRAM Timing register 1 */ |
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u32 sdtr2; /* SDRAM Timing register 2 */ |
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u32 sdcmr; /* SDRAM Mode register */ |
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u32 sdrtr; /* SDRAM Refresh timing register */ |
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u32 sdsr; /* SDRAM Status register */ |
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}; |
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/* |
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* NOR/PSRAM Control register BCR1 |
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* FMC controller Enable, only availabe for H7 |
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*/ |
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#define FMC_BCR1_FMCEN BIT(31) |
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/* Control register SDCR */ |
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#define FMC_SDCR_RPIPE_SHIFT 13 /* RPIPE bit shift */ |
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#define FMC_SDCR_RBURST_SHIFT 12 /* RBURST bit shift */ |
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#define FMC_SDCR_SDCLK_SHIFT 10 /* SDRAM clock divisor shift */ |
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#define FMC_SDCR_WP_SHIFT 9 /* Write protection shift */ |
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#define FMC_SDCR_CAS_SHIFT 7 /* CAS latency shift */ |
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#define FMC_SDCR_NB_SHIFT 6 /* Number of banks shift */ |
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#define FMC_SDCR_MWID_SHIFT 4 /* Memory width shift */ |
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#define FMC_SDCR_NR_SHIFT 2 /* Number of row address bits shift */ |
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#define FMC_SDCR_NC_SHIFT 0 /* Number of col address bits shift */ |
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/* Timings register SDTR */ |
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#define FMC_SDTR_TMRD_SHIFT 0 /* Load mode register to active */ |
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#define FMC_SDTR_TXSR_SHIFT 4 /* Exit self-refresh time */ |
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#define FMC_SDTR_TRAS_SHIFT 8 /* Self-refresh time */ |
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#define FMC_SDTR_TRC_SHIFT 12 /* Row cycle delay */ |
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#define FMC_SDTR_TWR_SHIFT 16 /* Recovery delay */ |
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#define FMC_SDTR_TRP_SHIFT 20 /* Row precharge delay */ |
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#define FMC_SDTR_TRCD_SHIFT 24 /* Row-to-column delay */ |
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#define FMC_SDCMR_NRFS_SHIFT 5 |
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#define FMC_SDCMR_MODE_NORMAL 0 |
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#define FMC_SDCMR_MODE_START_CLOCK 1 |
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#define FMC_SDCMR_MODE_PRECHARGE 2 |
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#define FMC_SDCMR_MODE_AUTOREFRESH 3 |
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#define FMC_SDCMR_MODE_WRITE_MODE 4 |
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#define FMC_SDCMR_MODE_SELFREFRESH 5 |
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#define FMC_SDCMR_MODE_POWERDOWN 6 |
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#define FMC_SDCMR_BANK_1 BIT(4) |
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#define FMC_SDCMR_BANK_2 BIT(3) |
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#define FMC_SDCMR_MODE_REGISTER_SHIFT 9 |
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#define FMC_SDSR_BUSY BIT(5) |
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#define FMC_BUSY_WAIT(regs) do { \ |
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__asm__ __volatile__ ("dsb" : : : "memory"); \ |
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while (regs->sdsr & FMC_SDSR_BUSY) \ |
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; \ |
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} while (0) |
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struct stm32_sdram_control { |
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u8 no_columns; |
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u8 no_rows; |
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u8 memory_width; |
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u8 no_banks; |
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u8 cas_latency; |
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u8 sdclk; |
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u8 rd_burst; |
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u8 rd_pipe_delay; |
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}; |
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struct stm32_sdram_timing { |
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u8 tmrd; |
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u8 txsr; |
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u8 tras; |
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u8 trc; |
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u8 trp; |
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u8 twr; |
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u8 trcd; |
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}; |
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enum stm32_fmc_bank { |
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SDRAM_BANK1, |
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SDRAM_BANK2, |
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MAX_SDRAM_BANK, |
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}; |
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enum stm32_fmc_family { |
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STM32F7_FMC, |
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STM32H7_FMC, |
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}; |
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struct bank_params { |
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struct stm32_sdram_control *sdram_control; |
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struct stm32_sdram_timing *sdram_timing; |
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u32 sdram_ref_count; |
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enum stm32_fmc_bank target_bank; |
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}; |
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struct stm32_sdram_params { |
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struct stm32_fmc_regs *base; |
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u8 no_sdram_banks; |
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struct bank_params bank_params[MAX_SDRAM_BANK]; |
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enum stm32_fmc_family family; |
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}; |
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#define SDRAM_MODE_BL_SHIFT 0 |
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#define SDRAM_MODE_CAS_SHIFT 4 |
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#define SDRAM_MODE_BL 0 |
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int stm32_sdram_init(struct udevice *dev) |
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{ |
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struct stm32_sdram_params *params = dev_get_platdata(dev); |
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struct stm32_sdram_control *control; |
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struct stm32_sdram_timing *timing; |
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struct stm32_fmc_regs *regs = params->base; |
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enum stm32_fmc_bank target_bank; |
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u32 ctb; /* SDCMR register: Command Target Bank */ |
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u32 ref_count; |
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u8 i; |
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/* disable the FMC controller */ |
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if (params->family == STM32H7_FMC) |
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clrbits_le32(®s->bcr1, FMC_BCR1_FMCEN); |
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for (i = 0; i < params->no_sdram_banks; i++) { |
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control = params->bank_params[i].sdram_control; |
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timing = params->bank_params[i].sdram_timing; |
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target_bank = params->bank_params[i].target_bank; |
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ref_count = params->bank_params[i].sdram_ref_count; |
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writel(control->sdclk << FMC_SDCR_SDCLK_SHIFT |
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| control->cas_latency << FMC_SDCR_CAS_SHIFT |
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| control->no_banks << FMC_SDCR_NB_SHIFT |
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| control->memory_width << FMC_SDCR_MWID_SHIFT |
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| control->no_rows << FMC_SDCR_NR_SHIFT |
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| control->no_columns << FMC_SDCR_NC_SHIFT |
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| control->rd_pipe_delay << FMC_SDCR_RPIPE_SHIFT |
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| control->rd_burst << FMC_SDCR_RBURST_SHIFT, |
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®s->sdcr1); |
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if (target_bank == SDRAM_BANK2) |
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writel(control->cas_latency << FMC_SDCR_CAS_SHIFT |
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| control->no_banks << FMC_SDCR_NB_SHIFT |
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| control->memory_width << FMC_SDCR_MWID_SHIFT |
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| control->no_rows << FMC_SDCR_NR_SHIFT |
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| control->no_columns << FMC_SDCR_NC_SHIFT, |
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®s->sdcr2); |
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writel(timing->trcd << FMC_SDTR_TRCD_SHIFT |
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| timing->trp << FMC_SDTR_TRP_SHIFT |
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| timing->twr << FMC_SDTR_TWR_SHIFT |
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| timing->trc << FMC_SDTR_TRC_SHIFT |
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| timing->tras << FMC_SDTR_TRAS_SHIFT |
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| timing->txsr << FMC_SDTR_TXSR_SHIFT |
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| timing->tmrd << FMC_SDTR_TMRD_SHIFT, |
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®s->sdtr1); |
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if (target_bank == SDRAM_BANK2) |
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writel(timing->trcd << FMC_SDTR_TRCD_SHIFT |
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| timing->trp << FMC_SDTR_TRP_SHIFT |
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| timing->twr << FMC_SDTR_TWR_SHIFT |
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| timing->trc << FMC_SDTR_TRC_SHIFT |
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| timing->tras << FMC_SDTR_TRAS_SHIFT |
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| timing->txsr << FMC_SDTR_TXSR_SHIFT |
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| timing->tmrd << FMC_SDTR_TMRD_SHIFT, |
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®s->sdtr2); |
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if (target_bank == SDRAM_BANK1) |
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ctb = FMC_SDCMR_BANK_1; |
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else |
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ctb = FMC_SDCMR_BANK_2; |
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writel(ctb | FMC_SDCMR_MODE_START_CLOCK, ®s->sdcmr); |
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udelay(200); /* 200 us delay, page 10, "Power-Up" */ |
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FMC_BUSY_WAIT(regs); |
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writel(ctb | FMC_SDCMR_MODE_PRECHARGE, ®s->sdcmr); |
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udelay(100); |
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FMC_BUSY_WAIT(regs); |
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writel((ctb | FMC_SDCMR_MODE_AUTOREFRESH | 7 << FMC_SDCMR_NRFS_SHIFT), |
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®s->sdcmr); |
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udelay(100); |
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FMC_BUSY_WAIT(regs); |
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writel(ctb | (SDRAM_MODE_BL << SDRAM_MODE_BL_SHIFT |
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| control->cas_latency << SDRAM_MODE_CAS_SHIFT) |
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<< FMC_SDCMR_MODE_REGISTER_SHIFT | FMC_SDCMR_MODE_WRITE_MODE, |
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®s->sdcmr); |
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udelay(100); |
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FMC_BUSY_WAIT(regs); |
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writel(ctb | FMC_SDCMR_MODE_NORMAL, ®s->sdcmr); |
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FMC_BUSY_WAIT(regs); |
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/* Refresh timer */ |
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writel(ref_count << 1, ®s->sdrtr); |
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} |
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/* enable the FMC controller */ |
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if (params->family == STM32H7_FMC) |
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setbits_le32(®s->bcr1, FMC_BCR1_FMCEN); |
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return 0; |
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} |
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static int stm32_fmc_ofdata_to_platdata(struct udevice *dev) |
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{ |
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struct stm32_sdram_params *params = dev_get_platdata(dev); |
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struct bank_params *bank_params; |
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struct ofnode_phandle_args args; |
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u32 *syscfg_base; |
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u32 mem_remap; |
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u32 swp_fmc; |
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ofnode bank_node; |
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char *bank_name; |
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u8 bank = 0; |
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int ret; |
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ret = dev_read_phandle_with_args(dev, "st,syscfg", NULL, 0, 0, |
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&args); |
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if (ret) { |
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dev_dbg(dev, "%s: can't find syscon device (%d)\n", __func__, ret); |
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} else { |
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syscfg_base = (u32 *)ofnode_get_addr(args.node); |
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mem_remap = dev_read_u32_default(dev, "st,mem_remap", NOT_FOUND); |
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if (mem_remap != NOT_FOUND) { |
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/* set memory mapping selection */ |
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clrsetbits_le32(syscfg_base, MEM_MODE_MASK, mem_remap); |
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} else { |
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dev_dbg(dev, "%s: cannot find st,mem_remap property\n", __func__); |
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} |
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swp_fmc = dev_read_u32_default(dev, "st,swp_fmc", NOT_FOUND); |
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if (swp_fmc != NOT_FOUND) { |
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/* set fmc swapping selection */ |
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clrsetbits_le32(syscfg_base, SWP_FMC_MASK, swp_fmc << SWP_FMC_OFFSET); |
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} else { |
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dev_dbg(dev, "%s: cannot find st,swp_fmc property\n", __func__); |
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} |
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dev_dbg(dev, "syscfg %x = %x\n", (u32)syscfg_base, *syscfg_base); |
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} |
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dev_for_each_subnode(bank_node, dev) { |
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/* extract the bank index from DT */ |
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bank_name = (char *)ofnode_get_name(bank_node); |
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strsep(&bank_name, "@"); |
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if (!bank_name) { |
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pr_err("missing sdram bank index"); |
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return -EINVAL; |
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} |
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bank_params = ¶ms->bank_params[bank]; |
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strict_strtoul(bank_name, 10, |
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(long unsigned int *)&bank_params->target_bank); |
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if (bank_params->target_bank >= MAX_SDRAM_BANK) { |
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pr_err("Found bank %d , but only bank 0 and 1 are supported", |
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bank_params->target_bank); |
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return -EINVAL; |
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} |
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debug("Find bank %s %u\n", bank_name, bank_params->target_bank); |
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params->bank_params[bank].sdram_control = |
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(struct stm32_sdram_control *) |
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ofnode_read_u8_array_ptr(bank_node, |
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"st,sdram-control", |
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sizeof(struct stm32_sdram_control)); |
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if (!params->bank_params[bank].sdram_control) { |
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pr_err("st,sdram-control not found for %s", |
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ofnode_get_name(bank_node)); |
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return -EINVAL; |
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} |
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params->bank_params[bank].sdram_timing = |
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(struct stm32_sdram_timing *) |
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ofnode_read_u8_array_ptr(bank_node, |
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"st,sdram-timing", |
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sizeof(struct stm32_sdram_timing)); |
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if (!params->bank_params[bank].sdram_timing) { |
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pr_err("st,sdram-timing not found for %s", |
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ofnode_get_name(bank_node)); |
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return -EINVAL; |
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} |
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bank_params->sdram_ref_count = ofnode_read_u32_default(bank_node, |
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"st,sdram-refcount", 8196); |
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bank++; |
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} |
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params->no_sdram_banks = bank; |
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debug("%s, no of banks = %d\n", __func__, params->no_sdram_banks); |
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return 0; |
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} |
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static int stm32_fmc_probe(struct udevice *dev) |
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{ |
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struct stm32_sdram_params *params = dev_get_platdata(dev); |
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int ret; |
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fdt_addr_t addr; |
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addr = dev_read_addr(dev); |
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if (addr == FDT_ADDR_T_NONE) |
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return -EINVAL; |
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params->base = (struct stm32_fmc_regs *)addr; |
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params->family = dev_get_driver_data(dev); |
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#ifdef CONFIG_CLK |
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struct clk clk; |
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ret = clk_get_by_index(dev, 0, &clk); |
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if (ret < 0) |
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return ret; |
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ret = clk_enable(&clk); |
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if (ret) { |
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dev_err(dev, "failed to enable clock\n"); |
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return ret; |
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} |
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#endif |
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ret = stm32_sdram_init(dev); |
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if (ret) |
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return ret; |
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return 0; |
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} |
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static int stm32_fmc_get_info(struct udevice *dev, struct ram_info *info) |
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{ |
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return 0; |
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} |
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static struct ram_ops stm32_fmc_ops = { |
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.get_info = stm32_fmc_get_info, |
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}; |
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static const struct udevice_id stm32_fmc_ids[] = { |
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{ .compatible = "st,stm32-fmc", .data = STM32F7_FMC }, |
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{ .compatible = "st,stm32h7-fmc", .data = STM32H7_FMC }, |
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{ } |
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}; |
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U_BOOT_DRIVER(stm32_fmc) = { |
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.name = "stm32_fmc", |
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.id = UCLASS_RAM, |
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.of_match = stm32_fmc_ids, |
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.ops = &stm32_fmc_ops, |
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.ofdata_to_platdata = stm32_fmc_ofdata_to_platdata, |
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.probe = stm32_fmc_probe, |
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.platdata_auto_alloc_size = sizeof(struct stm32_sdram_params), |
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};
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