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335 lines
7.8 KiB
335 lines
7.8 KiB
// SPDX-License-Identifier: GPL-2.0+ |
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/* |
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* (C) Copyright 2013 - 2015 Xilinx, Inc. |
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* |
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* Xilinx Zynq SD Host Controller Interface |
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*/ |
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#include <clk.h> |
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#include <common.h> |
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#include <dm.h> |
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#include <fdtdec.h> |
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#include "mmc_private.h" |
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#include <linux/libfdt.h> |
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#include <malloc.h> |
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#include <sdhci.h> |
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#include <zynqmp_tap_delay.h> |
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DECLARE_GLOBAL_DATA_PTR; |
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struct arasan_sdhci_plat { |
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struct mmc_config cfg; |
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struct mmc mmc; |
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unsigned int f_max; |
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}; |
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struct arasan_sdhci_priv { |
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struct sdhci_host *host; |
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u8 deviceid; |
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u8 bank; |
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u8 no_1p8; |
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bool pwrseq; |
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}; |
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#if defined(CONFIG_ARCH_ZYNQMP) |
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#define MMC_HS200_BUS_SPEED 5 |
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static const u8 mode2timing[] = { |
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[MMC_LEGACY] = UHS_SDR12_BUS_SPEED, |
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[SD_LEGACY] = UHS_SDR12_BUS_SPEED, |
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[MMC_HS] = HIGH_SPEED_BUS_SPEED, |
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[SD_HS] = HIGH_SPEED_BUS_SPEED, |
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[MMC_HS_52] = HIGH_SPEED_BUS_SPEED, |
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[MMC_DDR_52] = HIGH_SPEED_BUS_SPEED, |
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[UHS_SDR12] = UHS_SDR12_BUS_SPEED, |
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[UHS_SDR25] = UHS_SDR25_BUS_SPEED, |
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[UHS_SDR50] = UHS_SDR50_BUS_SPEED, |
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[UHS_DDR50] = UHS_DDR50_BUS_SPEED, |
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[UHS_SDR104] = UHS_SDR104_BUS_SPEED, |
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[MMC_HS_200] = MMC_HS200_BUS_SPEED, |
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}; |
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#define SDHCI_HOST_CTRL2 0x3E |
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#define SDHCI_CTRL2_MODE_MASK 0x7 |
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#define SDHCI_18V_SIGNAL 0x8 |
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#define SDHCI_CTRL_EXEC_TUNING 0x0040 |
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#define SDHCI_CTRL_TUNED_CLK 0x80 |
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#define SDHCI_TUNING_LOOP_COUNT 40 |
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static void arasan_zynqmp_dll_reset(struct sdhci_host *host, u8 deviceid) |
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{ |
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u16 clk; |
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unsigned long timeout; |
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clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL); |
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clk &= ~(SDHCI_CLOCK_CARD_EN); |
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sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); |
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/* Issue DLL Reset */ |
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zynqmp_dll_reset(deviceid); |
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/* Wait max 20 ms */ |
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timeout = 100; |
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while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL)) |
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& SDHCI_CLOCK_INT_STABLE)) { |
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if (timeout == 0) { |
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dev_err(mmc_dev(host->mmc), |
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": Internal clock never stabilised.\n"); |
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return; |
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} |
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timeout--; |
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udelay(1000); |
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} |
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clk |= SDHCI_CLOCK_CARD_EN; |
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sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); |
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} |
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static int arasan_sdhci_execute_tuning(struct mmc *mmc, u8 opcode) |
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{ |
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struct mmc_cmd cmd; |
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struct mmc_data data; |
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u32 ctrl; |
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struct sdhci_host *host; |
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struct arasan_sdhci_priv *priv = dev_get_priv(mmc->dev); |
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char tuning_loop_counter = SDHCI_TUNING_LOOP_COUNT; |
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u8 deviceid; |
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debug("%s\n", __func__); |
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host = priv->host; |
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deviceid = priv->deviceid; |
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ctrl = sdhci_readw(host, SDHCI_HOST_CTRL2); |
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ctrl |= SDHCI_CTRL_EXEC_TUNING; |
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sdhci_writew(host, ctrl, SDHCI_HOST_CTRL2); |
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mdelay(1); |
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arasan_zynqmp_dll_reset(host, deviceid); |
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sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_INT_ENABLE); |
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sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_SIGNAL_ENABLE); |
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do { |
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cmd.cmdidx = opcode; |
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cmd.resp_type = MMC_RSP_R1; |
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cmd.cmdarg = 0; |
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data.blocksize = 64; |
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data.blocks = 1; |
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data.flags = MMC_DATA_READ; |
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if (tuning_loop_counter-- == 0) |
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break; |
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if (cmd.cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200 && |
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mmc->bus_width == 8) |
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data.blocksize = 128; |
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sdhci_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG, |
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data.blocksize), |
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SDHCI_BLOCK_SIZE); |
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sdhci_writew(host, data.blocks, SDHCI_BLOCK_COUNT); |
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sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE); |
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mmc_send_cmd(mmc, &cmd, NULL); |
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ctrl = sdhci_readw(host, SDHCI_HOST_CTRL2); |
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if (cmd.cmdidx == MMC_CMD_SEND_TUNING_BLOCK) |
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udelay(1); |
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} while (ctrl & SDHCI_CTRL_EXEC_TUNING); |
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if (tuning_loop_counter < 0) { |
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ctrl &= ~SDHCI_CTRL_TUNED_CLK; |
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sdhci_writel(host, ctrl, SDHCI_HOST_CTRL2); |
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} |
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if (!(ctrl & SDHCI_CTRL_TUNED_CLK)) { |
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printf("%s:Tuning failed\n", __func__); |
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return -1; |
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} |
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udelay(1); |
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arasan_zynqmp_dll_reset(host, deviceid); |
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/* Enable only interrupts served by the SD controller */ |
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sdhci_writel(host, SDHCI_INT_DATA_MASK | SDHCI_INT_CMD_MASK, |
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SDHCI_INT_ENABLE); |
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/* Mask all sdhci interrupt sources */ |
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sdhci_writel(host, 0x0, SDHCI_SIGNAL_ENABLE); |
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return 0; |
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} |
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static void arasan_sdhci_set_tapdelay(struct sdhci_host *host) |
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{ |
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struct arasan_sdhci_priv *priv = dev_get_priv(host->mmc->dev); |
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struct mmc *mmc = (struct mmc *)host->mmc; |
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u8 uhsmode; |
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uhsmode = mode2timing[mmc->selected_mode]; |
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if (uhsmode >= UHS_SDR25_BUS_SPEED) |
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arasan_zynqmp_set_tapdelay(priv->deviceid, uhsmode, |
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priv->bank); |
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} |
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static void arasan_sdhci_set_control_reg(struct sdhci_host *host) |
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{ |
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struct mmc *mmc = (struct mmc *)host->mmc; |
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u32 reg; |
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if (!IS_SD(mmc)) |
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return; |
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if (mmc->signal_voltage == MMC_SIGNAL_VOLTAGE_180) { |
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reg = sdhci_readw(host, SDHCI_HOST_CTRL2); |
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reg |= SDHCI_18V_SIGNAL; |
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sdhci_writew(host, reg, SDHCI_HOST_CTRL2); |
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} |
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if (mmc->selected_mode > SD_HS && |
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mmc->selected_mode <= UHS_DDR50) { |
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reg = sdhci_readw(host, SDHCI_HOST_CTRL2); |
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reg &= ~SDHCI_CTRL2_MODE_MASK; |
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switch (mmc->selected_mode) { |
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case UHS_SDR12: |
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reg |= UHS_SDR12_BUS_SPEED; |
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break; |
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case UHS_SDR25: |
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reg |= UHS_SDR25_BUS_SPEED; |
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break; |
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case UHS_SDR50: |
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reg |= UHS_SDR50_BUS_SPEED; |
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break; |
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case UHS_SDR104: |
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reg |= UHS_SDR104_BUS_SPEED; |
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break; |
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case UHS_DDR50: |
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reg |= UHS_DDR50_BUS_SPEED; |
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break; |
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default: |
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break; |
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} |
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sdhci_writew(host, reg, SDHCI_HOST_CTRL2); |
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} |
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} |
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#endif |
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#if defined(CONFIG_DM_MMC) && defined(CONFIG_ARCH_ZYNQMP) |
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const struct sdhci_ops arasan_ops = { |
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.platform_execute_tuning = &arasan_sdhci_execute_tuning, |
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.set_delay = &arasan_sdhci_set_tapdelay, |
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.set_control_reg = &arasan_sdhci_set_control_reg, |
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}; |
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#endif |
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static int arasan_sdhci_probe(struct udevice *dev) |
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{ |
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struct arasan_sdhci_plat *plat = dev_get_platdata(dev); |
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struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev); |
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struct arasan_sdhci_priv *priv = dev_get_priv(dev); |
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struct sdhci_host *host; |
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struct clk clk; |
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unsigned long clock; |
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int ret; |
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host = priv->host; |
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ret = clk_get_by_index(dev, 0, &clk); |
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if (ret < 0) { |
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dev_err(dev, "failed to get clock\n"); |
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return ret; |
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} |
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clock = clk_get_rate(&clk); |
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if (IS_ERR_VALUE(clock)) { |
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dev_err(dev, "failed to get rate\n"); |
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return clock; |
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} |
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debug("%s: CLK %ld\n", __func__, clock); |
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ret = clk_enable(&clk); |
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if (ret && ret != -ENOSYS) { |
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dev_err(dev, "failed to enable clock\n"); |
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return ret; |
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} |
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host->quirks = SDHCI_QUIRK_WAIT_SEND_CMD | |
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SDHCI_QUIRK_BROKEN_R1B; |
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#ifdef CONFIG_ZYNQ_HISPD_BROKEN |
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host->quirks |= SDHCI_QUIRK_BROKEN_HISPD_MODE; |
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#endif |
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if (priv->no_1p8) |
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host->quirks |= SDHCI_QUIRK_NO_1_8_V; |
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host->max_clk = clock; |
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ret = sdhci_setup_cfg(&plat->cfg, host, plat->f_max, |
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CONFIG_ZYNQ_SDHCI_MIN_FREQ); |
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host->mmc = &plat->mmc; |
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if (ret) |
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return ret; |
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host->mmc->priv = host; |
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host->mmc->dev = dev; |
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upriv->mmc = host->mmc; |
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return sdhci_probe(dev); |
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} |
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static int arasan_sdhci_ofdata_to_platdata(struct udevice *dev) |
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{ |
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struct arasan_sdhci_plat *plat = dev_get_platdata(dev); |
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struct arasan_sdhci_priv *priv = dev_get_priv(dev); |
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priv->host = calloc(1, sizeof(struct sdhci_host)); |
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if (!priv->host) |
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return -1; |
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priv->host->name = dev->name; |
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#if defined(CONFIG_DM_MMC) && defined(CONFIG_ARCH_ZYNQMP) |
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priv->host->ops = &arasan_ops; |
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#endif |
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priv->host->ioaddr = (void *)dev_read_addr(dev); |
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if (IS_ERR(priv->host->ioaddr)) |
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return PTR_ERR(priv->host->ioaddr); |
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priv->deviceid = dev_read_u32_default(dev, "xlnx,device_id", -1); |
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priv->bank = dev_read_u32_default(dev, "xlnx,mio_bank", -1); |
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priv->no_1p8 = dev_read_bool(dev, "no-1-8-v"); |
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plat->f_max = dev_read_u32_default(dev, "max-frequency", |
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CONFIG_ZYNQ_SDHCI_MAX_FREQ); |
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return 0; |
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} |
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static int arasan_sdhci_bind(struct udevice *dev) |
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{ |
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struct arasan_sdhci_plat *plat = dev_get_platdata(dev); |
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return sdhci_bind(dev, &plat->mmc, &plat->cfg); |
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} |
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static const struct udevice_id arasan_sdhci_ids[] = { |
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{ .compatible = "arasan,sdhci-8.9a" }, |
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{ } |
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}; |
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U_BOOT_DRIVER(arasan_sdhci_drv) = { |
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.name = "arasan_sdhci", |
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.id = UCLASS_MMC, |
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.of_match = arasan_sdhci_ids, |
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.ofdata_to_platdata = arasan_sdhci_ofdata_to_platdata, |
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.ops = &sdhci_ops, |
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.bind = arasan_sdhci_bind, |
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.probe = arasan_sdhci_probe, |
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.priv_auto_alloc_size = sizeof(struct arasan_sdhci_priv), |
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.platdata_auto_alloc_size = sizeof(struct arasan_sdhci_plat), |
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};
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