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293 lines
7.0 KiB
293 lines
7.0 KiB
// SPDX-License-Identifier: GPL-2.0+ |
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/* |
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* (C) Copyright 2016 Carlo Caione <[email protected]> |
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*/ |
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#include <common.h> |
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#include <dm.h> |
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#include <fdtdec.h> |
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#include <malloc.h> |
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#include <mmc.h> |
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#include <asm/io.h> |
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#include <asm/arch/sd_emmc.h> |
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#include <linux/log2.h> |
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static inline void *get_regbase(const struct mmc *mmc) |
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{ |
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struct meson_mmc_platdata *pdata = mmc->priv; |
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return pdata->regbase; |
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} |
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static inline uint32_t meson_read(struct mmc *mmc, int offset) |
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{ |
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return readl(get_regbase(mmc) + offset); |
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} |
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static inline void meson_write(struct mmc *mmc, uint32_t val, int offset) |
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{ |
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writel(val, get_regbase(mmc) + offset); |
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} |
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static void meson_mmc_config_clock(struct mmc *mmc) |
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{ |
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uint32_t meson_mmc_clk = 0; |
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unsigned int clk, clk_src, clk_div; |
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if (!mmc->clock) |
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return; |
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/* 1GHz / CLK_MAX_DIV = 15,9 MHz */ |
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if (mmc->clock > 16000000) { |
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clk = SD_EMMC_CLKSRC_DIV2; |
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clk_src = CLK_SRC_DIV2; |
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} else { |
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clk = SD_EMMC_CLKSRC_24M; |
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clk_src = CLK_SRC_24M; |
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} |
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clk_div = DIV_ROUND_UP(clk, mmc->clock); |
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/* 180 phase core clock */ |
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meson_mmc_clk |= CLK_CO_PHASE_180; |
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/* 180 phase tx clock */ |
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meson_mmc_clk |= CLK_TX_PHASE_000; |
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/* clock settings */ |
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meson_mmc_clk |= clk_src; |
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meson_mmc_clk |= clk_div; |
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meson_write(mmc, meson_mmc_clk, MESON_SD_EMMC_CLOCK); |
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} |
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static int meson_dm_mmc_set_ios(struct udevice *dev) |
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{ |
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struct mmc *mmc = mmc_get_mmc_dev(dev); |
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uint32_t meson_mmc_cfg; |
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meson_mmc_config_clock(mmc); |
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meson_mmc_cfg = meson_read(mmc, MESON_SD_EMMC_CFG); |
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meson_mmc_cfg &= ~CFG_BUS_WIDTH_MASK; |
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if (mmc->bus_width == 1) |
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meson_mmc_cfg |= CFG_BUS_WIDTH_1; |
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else if (mmc->bus_width == 4) |
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meson_mmc_cfg |= CFG_BUS_WIDTH_4; |
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else if (mmc->bus_width == 8) |
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meson_mmc_cfg |= CFG_BUS_WIDTH_8; |
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else |
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return -EINVAL; |
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/* 512 bytes block length */ |
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meson_mmc_cfg &= ~CFG_BL_LEN_MASK; |
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meson_mmc_cfg |= CFG_BL_LEN_512; |
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/* Response timeout 256 clk */ |
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meson_mmc_cfg &= ~CFG_RESP_TIMEOUT_MASK; |
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meson_mmc_cfg |= CFG_RESP_TIMEOUT_256; |
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/* Command-command gap 16 clk */ |
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meson_mmc_cfg &= ~CFG_RC_CC_MASK; |
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meson_mmc_cfg |= CFG_RC_CC_16; |
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meson_write(mmc, meson_mmc_cfg, MESON_SD_EMMC_CFG); |
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return 0; |
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} |
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static void meson_mmc_setup_cmd(struct mmc *mmc, struct mmc_data *data, |
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struct mmc_cmd *cmd) |
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{ |
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uint32_t meson_mmc_cmd = 0, cfg; |
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meson_mmc_cmd |= cmd->cmdidx << CMD_CFG_CMD_INDEX_SHIFT; |
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if (cmd->resp_type & MMC_RSP_PRESENT) { |
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if (cmd->resp_type & MMC_RSP_136) |
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meson_mmc_cmd |= CMD_CFG_RESP_128; |
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if (cmd->resp_type & MMC_RSP_BUSY) |
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meson_mmc_cmd |= CMD_CFG_R1B; |
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if (!(cmd->resp_type & MMC_RSP_CRC)) |
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meson_mmc_cmd |= CMD_CFG_RESP_NOCRC; |
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} else { |
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meson_mmc_cmd |= CMD_CFG_NO_RESP; |
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} |
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if (data) { |
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cfg = meson_read(mmc, MESON_SD_EMMC_CFG); |
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cfg &= ~CFG_BL_LEN_MASK; |
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cfg |= ilog2(data->blocksize) << CFG_BL_LEN_SHIFT; |
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meson_write(mmc, cfg, MESON_SD_EMMC_CFG); |
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if (data->flags == MMC_DATA_WRITE) |
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meson_mmc_cmd |= CMD_CFG_DATA_WR; |
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meson_mmc_cmd |= CMD_CFG_DATA_IO | CMD_CFG_BLOCK_MODE | |
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data->blocks; |
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} |
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meson_mmc_cmd |= CMD_CFG_TIMEOUT_4S | CMD_CFG_OWNER | |
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CMD_CFG_END_OF_CHAIN; |
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meson_write(mmc, meson_mmc_cmd, MESON_SD_EMMC_CMD_CFG); |
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} |
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static void meson_mmc_setup_addr(struct mmc *mmc, struct mmc_data *data) |
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{ |
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struct meson_mmc_platdata *pdata = mmc->priv; |
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unsigned int data_size; |
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uint32_t data_addr = 0; |
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if (data) { |
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data_size = data->blocks * data->blocksize; |
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if (data->flags == MMC_DATA_READ) { |
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data_addr = (ulong) data->dest; |
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invalidate_dcache_range(data_addr, |
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data_addr + data_size); |
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} else { |
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pdata->w_buf = calloc(data_size, sizeof(char)); |
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data_addr = (ulong) pdata->w_buf; |
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memcpy(pdata->w_buf, data->src, data_size); |
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flush_dcache_range(data_addr, data_addr + data_size); |
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} |
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} |
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meson_write(mmc, data_addr, MESON_SD_EMMC_CMD_DAT); |
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} |
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static void meson_mmc_read_response(struct mmc *mmc, struct mmc_cmd *cmd) |
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{ |
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if (cmd->resp_type & MMC_RSP_136) { |
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cmd->response[0] = meson_read(mmc, MESON_SD_EMMC_CMD_RSP3); |
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cmd->response[1] = meson_read(mmc, MESON_SD_EMMC_CMD_RSP2); |
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cmd->response[2] = meson_read(mmc, MESON_SD_EMMC_CMD_RSP1); |
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cmd->response[3] = meson_read(mmc, MESON_SD_EMMC_CMD_RSP); |
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} else { |
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cmd->response[0] = meson_read(mmc, MESON_SD_EMMC_CMD_RSP); |
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} |
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} |
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static int meson_dm_mmc_send_cmd(struct udevice *dev, struct mmc_cmd *cmd, |
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struct mmc_data *data) |
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{ |
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struct mmc *mmc = mmc_get_mmc_dev(dev); |
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struct meson_mmc_platdata *pdata = mmc->priv; |
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uint32_t status; |
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ulong start; |
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int ret = 0; |
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/* max block size supported by chip is 512 byte */ |
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if (data && data->blocksize > 512) |
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return -EINVAL; |
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meson_mmc_setup_cmd(mmc, data, cmd); |
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meson_mmc_setup_addr(mmc, data); |
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meson_write(mmc, cmd->cmdarg, MESON_SD_EMMC_CMD_ARG); |
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/* use 10s timeout */ |
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start = get_timer(0); |
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do { |
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status = meson_read(mmc, MESON_SD_EMMC_STATUS); |
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} while(!(status & STATUS_END_OF_CHAIN) && get_timer(start) < 10000); |
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if (!(status & STATUS_END_OF_CHAIN)) |
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ret = -ETIMEDOUT; |
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else if (status & STATUS_RESP_TIMEOUT) |
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ret = -ETIMEDOUT; |
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else if (status & STATUS_ERR_MASK) |
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ret = -EIO; |
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meson_mmc_read_response(mmc, cmd); |
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if (data && data->flags == MMC_DATA_WRITE) |
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free(pdata->w_buf); |
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/* reset status bits */ |
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meson_write(mmc, STATUS_MASK, MESON_SD_EMMC_STATUS); |
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return ret; |
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} |
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static const struct dm_mmc_ops meson_dm_mmc_ops = { |
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.send_cmd = meson_dm_mmc_send_cmd, |
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.set_ios = meson_dm_mmc_set_ios, |
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}; |
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static int meson_mmc_ofdata_to_platdata(struct udevice *dev) |
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{ |
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struct meson_mmc_platdata *pdata = dev_get_platdata(dev); |
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fdt_addr_t addr; |
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addr = devfdt_get_addr(dev); |
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if (addr == FDT_ADDR_T_NONE) |
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return -EINVAL; |
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pdata->regbase = (void *)addr; |
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return 0; |
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} |
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static int meson_mmc_probe(struct udevice *dev) |
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{ |
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struct meson_mmc_platdata *pdata = dev_get_platdata(dev); |
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struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev); |
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struct mmc *mmc = &pdata->mmc; |
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struct mmc_config *cfg = &pdata->cfg; |
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uint32_t val; |
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cfg->voltages = MMC_VDD_33_34 | MMC_VDD_32_33 | |
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MMC_VDD_31_32 | MMC_VDD_165_195; |
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cfg->host_caps = MMC_MODE_8BIT | MMC_MODE_4BIT | |
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MMC_MODE_HS_52MHz | MMC_MODE_HS; |
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cfg->f_min = DIV_ROUND_UP(SD_EMMC_CLKSRC_24M, CLK_MAX_DIV); |
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cfg->f_max = 100000000; /* 100 MHz */ |
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cfg->b_max = 511; /* max 512 - 1 blocks */ |
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cfg->name = dev->name; |
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mmc->priv = pdata; |
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upriv->mmc = mmc; |
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mmc_set_clock(mmc, cfg->f_min, MMC_CLK_ENABLE); |
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/* reset all status bits */ |
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meson_write(mmc, STATUS_MASK, MESON_SD_EMMC_STATUS); |
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/* disable interrupts */ |
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meson_write(mmc, 0, MESON_SD_EMMC_IRQ_EN); |
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/* enable auto clock mode */ |
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val = meson_read(mmc, MESON_SD_EMMC_CFG); |
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val &= ~CFG_SDCLK_ALWAYS_ON; |
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val |= CFG_AUTO_CLK; |
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meson_write(mmc, val, MESON_SD_EMMC_CFG); |
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return 0; |
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} |
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int meson_mmc_bind(struct udevice *dev) |
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{ |
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struct meson_mmc_platdata *pdata = dev_get_platdata(dev); |
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return mmc_bind(dev, &pdata->mmc, &pdata->cfg); |
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} |
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static const struct udevice_id meson_mmc_match[] = { |
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{ .compatible = "amlogic,meson-gx-mmc" }, |
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{ /* sentinel */ } |
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}; |
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U_BOOT_DRIVER(meson_mmc) = { |
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.name = "meson_gx_mmc", |
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.id = UCLASS_MMC, |
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.of_match = meson_mmc_match, |
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.ops = &meson_dm_mmc_ops, |
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.probe = meson_mmc_probe, |
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.bind = meson_mmc_bind, |
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.ofdata_to_platdata = meson_mmc_ofdata_to_platdata, |
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.platdata_auto_alloc_size = sizeof(struct meson_mmc_platdata), |
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};
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