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480 lines
11 KiB
480 lines
11 KiB
// SPDX-License-Identifier: GPL-2.0+ |
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/* |
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* Faraday MMC/SD Host Controller |
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* |
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* (C) Copyright 2010 Faraday Technology |
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* Dante Su <[email protected]> |
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* |
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* Copyright 2018 Andes Technology, Inc. |
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* Author: Rick Chen ([email protected]) |
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*/ |
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#include <common.h> |
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#include <clk.h> |
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#include <malloc.h> |
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#include <part.h> |
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#include <mmc.h> |
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#include <linux/io.h> |
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#include <linux/errno.h> |
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#include <asm/byteorder.h> |
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#include <faraday/ftsdc010.h> |
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#include "ftsdc010_mci.h" |
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#include <dm.h> |
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#include <dt-structs.h> |
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#include <errno.h> |
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#include <mapmem.h> |
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#include <pwrseq.h> |
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#include <syscon.h> |
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#include <linux/err.h> |
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DECLARE_GLOBAL_DATA_PTR; |
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#define CFG_CMD_TIMEOUT (CONFIG_SYS_HZ >> 4) /* 250 ms */ |
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#define CFG_RST_TIMEOUT CONFIG_SYS_HZ /* 1 sec reset timeout */ |
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#if CONFIG_IS_ENABLED(OF_PLATDATA) |
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struct ftsdc010 { |
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fdt32_t bus_width; |
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bool cap_mmc_highspeed; |
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bool cap_sd_highspeed; |
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fdt32_t clock_freq_min_max[2]; |
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struct phandle_2_cell clocks[4]; |
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fdt32_t fifo_depth; |
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fdt32_t reg[2]; |
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}; |
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#endif |
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struct ftsdc010_plat { |
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#if CONFIG_IS_ENABLED(OF_PLATDATA) |
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struct ftsdc010 dtplat; |
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#endif |
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struct mmc_config cfg; |
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struct mmc mmc; |
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}; |
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struct ftsdc_priv { |
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struct clk clk; |
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struct ftsdc010_chip chip; |
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int fifo_depth; |
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bool fifo_mode; |
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u32 minmax[2]; |
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}; |
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static inline int ftsdc010_send_cmd(struct mmc *mmc, struct mmc_cmd *mmc_cmd) |
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{ |
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struct ftsdc010_chip *chip = mmc->priv; |
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struct ftsdc010_mmc __iomem *regs = chip->regs; |
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int ret = -ETIMEDOUT; |
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uint32_t ts, st; |
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uint32_t cmd = FTSDC010_CMD_IDX(mmc_cmd->cmdidx); |
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uint32_t arg = mmc_cmd->cmdarg; |
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uint32_t flags = mmc_cmd->resp_type; |
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cmd |= FTSDC010_CMD_CMD_EN; |
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if (chip->acmd) { |
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cmd |= FTSDC010_CMD_APP_CMD; |
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chip->acmd = 0; |
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} |
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if (flags & MMC_RSP_PRESENT) |
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cmd |= FTSDC010_CMD_NEED_RSP; |
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if (flags & MMC_RSP_136) |
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cmd |= FTSDC010_CMD_LONG_RSP; |
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writel(FTSDC010_STATUS_RSP_MASK | FTSDC010_STATUS_CMD_SEND, |
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®s->clr); |
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writel(arg, ®s->argu); |
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writel(cmd, ®s->cmd); |
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if (!(flags & (MMC_RSP_PRESENT | MMC_RSP_136))) { |
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for (ts = get_timer(0); get_timer(ts) < CFG_CMD_TIMEOUT; ) { |
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if (readl(®s->status) & FTSDC010_STATUS_CMD_SEND) { |
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writel(FTSDC010_STATUS_CMD_SEND, ®s->clr); |
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ret = 0; |
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break; |
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} |
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} |
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} else { |
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st = 0; |
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for (ts = get_timer(0); get_timer(ts) < CFG_CMD_TIMEOUT; ) { |
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st = readl(®s->status); |
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writel(st & FTSDC010_STATUS_RSP_MASK, ®s->clr); |
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if (st & FTSDC010_STATUS_RSP_MASK) |
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break; |
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} |
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if (st & FTSDC010_STATUS_RSP_CRC_OK) { |
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if (flags & MMC_RSP_136) { |
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mmc_cmd->response[0] = readl(®s->rsp3); |
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mmc_cmd->response[1] = readl(®s->rsp2); |
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mmc_cmd->response[2] = readl(®s->rsp1); |
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mmc_cmd->response[3] = readl(®s->rsp0); |
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} else { |
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mmc_cmd->response[0] = readl(®s->rsp0); |
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} |
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ret = 0; |
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} else { |
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debug("ftsdc010: rsp err (cmd=%d, st=0x%x)\n", |
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mmc_cmd->cmdidx, st); |
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} |
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} |
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if (ret) { |
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debug("ftsdc010: cmd timeout (op code=%d)\n", |
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mmc_cmd->cmdidx); |
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} else if (mmc_cmd->cmdidx == MMC_CMD_APP_CMD) { |
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chip->acmd = 1; |
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} |
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return ret; |
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} |
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static void ftsdc010_clkset(struct mmc *mmc, uint32_t rate) |
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{ |
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struct ftsdc010_chip *chip = mmc->priv; |
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struct ftsdc010_mmc __iomem *regs = chip->regs; |
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uint32_t div; |
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for (div = 0; div < 0x7f; ++div) { |
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if (rate >= chip->sclk / (2 * (div + 1))) |
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break; |
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} |
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chip->rate = chip->sclk / (2 * (div + 1)); |
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writel(FTSDC010_CCR_CLK_DIV(div), ®s->ccr); |
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if (IS_SD(mmc)) { |
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setbits_le32(®s->ccr, FTSDC010_CCR_CLK_SD); |
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if (chip->rate > 25000000) |
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setbits_le32(®s->ccr, FTSDC010_CCR_CLK_HISPD); |
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else |
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clrbits_le32(®s->ccr, FTSDC010_CCR_CLK_HISPD); |
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} |
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} |
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static int ftsdc010_wait(struct ftsdc010_mmc __iomem *regs, uint32_t mask) |
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{ |
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int ret = -ETIMEDOUT; |
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uint32_t st, timeout = 10000000; |
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while (timeout--) { |
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st = readl(®s->status); |
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if (!(st & mask)) |
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continue; |
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writel(st & mask, ®s->clr); |
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ret = 0; |
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break; |
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} |
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if (ret){ |
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debug("ftsdc010: wait st(0x%x) timeout\n", mask); |
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} |
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return ret; |
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} |
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/* |
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* u-boot mmc api |
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*/ |
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static int ftsdc010_request(struct udevice *dev, struct mmc_cmd *cmd, |
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struct mmc_data *data) |
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{ |
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struct mmc *mmc = mmc_get_mmc_dev(dev); |
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int ret = -EOPNOTSUPP; |
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uint32_t len = 0; |
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struct ftsdc010_chip *chip = mmc->priv; |
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struct ftsdc010_mmc __iomem *regs = chip->regs; |
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if (data && (data->flags & MMC_DATA_WRITE) && chip->wprot) { |
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printf("ftsdc010: the card is write protected!\n"); |
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return ret; |
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} |
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if (data) { |
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uint32_t dcr; |
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len = data->blocksize * data->blocks; |
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/* 1. data disable + fifo reset */ |
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dcr = 0; |
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#ifdef CONFIG_FTSDC010_SDIO |
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dcr |= FTSDC010_DCR_FIFO_RST; |
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#endif |
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writel(dcr, ®s->dcr); |
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/* 2. clear status register */ |
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writel(FTSDC010_STATUS_DATA_MASK | FTSDC010_STATUS_FIFO_URUN |
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| FTSDC010_STATUS_FIFO_ORUN, ®s->clr); |
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/* 3. data timeout (1 sec) */ |
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writel(chip->rate, ®s->dtr); |
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/* 4. data length (bytes) */ |
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writel(len, ®s->dlr); |
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/* 5. data enable */ |
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dcr = (ffs(data->blocksize) - 1) | FTSDC010_DCR_DATA_EN; |
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if (data->flags & MMC_DATA_WRITE) |
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dcr |= FTSDC010_DCR_DATA_WRITE; |
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writel(dcr, ®s->dcr); |
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} |
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ret = ftsdc010_send_cmd(mmc, cmd); |
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if (ret) { |
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printf("ftsdc010: CMD%d failed\n", cmd->cmdidx); |
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return ret; |
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} |
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if (!data) |
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return ret; |
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if (data->flags & MMC_DATA_WRITE) { |
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const uint8_t *buf = (const uint8_t *)data->src; |
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while (len > 0) { |
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int wlen; |
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/* wait for tx ready */ |
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ret = ftsdc010_wait(regs, FTSDC010_STATUS_FIFO_URUN); |
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if (ret) |
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break; |
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/* write bytes to ftsdc010 */ |
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for (wlen = 0; wlen < len && wlen < chip->fifo; ) { |
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writel(*(uint32_t *)buf, ®s->dwr); |
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buf += 4; |
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wlen += 4; |
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} |
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len -= wlen; |
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} |
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} else { |
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uint8_t *buf = (uint8_t *)data->dest; |
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while (len > 0) { |
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int rlen; |
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/* wait for rx ready */ |
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ret = ftsdc010_wait(regs, FTSDC010_STATUS_FIFO_ORUN); |
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if (ret) |
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break; |
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/* fetch bytes from ftsdc010 */ |
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for (rlen = 0; rlen < len && rlen < chip->fifo; ) { |
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*(uint32_t *)buf = readl(®s->dwr); |
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buf += 4; |
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rlen += 4; |
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} |
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len -= rlen; |
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} |
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} |
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if (!ret) { |
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ret = ftsdc010_wait(regs, |
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FTSDC010_STATUS_DATA_END | FTSDC010_STATUS_DATA_CRC_OK); |
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} |
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return ret; |
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} |
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static int ftsdc010_set_ios(struct udevice *dev) |
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{ |
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struct mmc *mmc = mmc_get_mmc_dev(dev); |
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struct ftsdc010_chip *chip = mmc->priv; |
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struct ftsdc010_mmc __iomem *regs = chip->regs; |
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ftsdc010_clkset(mmc, mmc->clock); |
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clrbits_le32(®s->bwr, FTSDC010_BWR_MODE_MASK); |
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switch (mmc->bus_width) { |
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case 4: |
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setbits_le32(®s->bwr, FTSDC010_BWR_MODE_4BIT); |
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break; |
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case 8: |
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setbits_le32(®s->bwr, FTSDC010_BWR_MODE_8BIT); |
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break; |
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default: |
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setbits_le32(®s->bwr, FTSDC010_BWR_MODE_1BIT); |
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break; |
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} |
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return 0; |
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} |
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static int ftsdc010_get_cd(struct udevice *dev) |
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{ |
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struct mmc *mmc = mmc_get_mmc_dev(dev); |
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struct ftsdc010_chip *chip = mmc->priv; |
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struct ftsdc010_mmc __iomem *regs = chip->regs; |
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return !(readl(®s->status) & FTSDC010_STATUS_CARD_DETECT); |
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} |
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static int ftsdc010_get_wp(struct udevice *dev) |
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{ |
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struct mmc *mmc = mmc_get_mmc_dev(dev); |
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struct ftsdc010_chip *chip = mmc->priv; |
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struct ftsdc010_mmc __iomem *regs = chip->regs; |
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if (readl(®s->status) & FTSDC010_STATUS_WRITE_PROT) { |
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printf("ftsdc010: write protected\n"); |
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chip->wprot = 1; |
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} |
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return 0; |
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} |
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static int ftsdc010_init(struct mmc *mmc) |
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{ |
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struct ftsdc010_chip *chip = mmc->priv; |
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struct ftsdc010_mmc __iomem *regs = chip->regs; |
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uint32_t ts; |
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chip->fifo = (readl(®s->feature) & 0xff) << 2; |
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/* 1. chip reset */ |
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writel(FTSDC010_CMD_SDC_RST, ®s->cmd); |
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for (ts = get_timer(0); get_timer(ts) < CFG_RST_TIMEOUT; ) { |
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if (readl(®s->cmd) & FTSDC010_CMD_SDC_RST) |
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continue; |
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break; |
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} |
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if (readl(®s->cmd) & FTSDC010_CMD_SDC_RST) { |
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printf("ftsdc010: reset failed\n"); |
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return -EOPNOTSUPP; |
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} |
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/* 2. enter low speed mode (400k card detection) */ |
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ftsdc010_clkset(mmc, 400000); |
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/* 3. interrupt disabled */ |
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writel(0, ®s->int_mask); |
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return 0; |
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} |
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static int ftsdc010_probe(struct udevice *dev) |
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{ |
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struct mmc *mmc = mmc_get_mmc_dev(dev); |
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return ftsdc010_init(mmc); |
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} |
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const struct dm_mmc_ops dm_ftsdc010_mmc_ops = { |
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.send_cmd = ftsdc010_request, |
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.set_ios = ftsdc010_set_ios, |
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.get_cd = ftsdc010_get_cd, |
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.get_wp = ftsdc010_get_wp, |
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}; |
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static void ftsdc_setup_cfg(struct mmc_config *cfg, const char *name, int buswidth, |
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uint caps, u32 max_clk, u32 min_clk) |
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{ |
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cfg->name = name; |
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cfg->f_min = min_clk; |
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cfg->f_max = max_clk; |
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cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195; |
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cfg->host_caps = caps; |
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if (buswidth == 8) { |
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cfg->host_caps |= MMC_MODE_8BIT; |
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cfg->host_caps &= ~MMC_MODE_4BIT; |
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} else { |
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cfg->host_caps |= MMC_MODE_4BIT; |
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cfg->host_caps &= ~MMC_MODE_8BIT; |
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} |
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cfg->part_type = PART_TYPE_DOS; |
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cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT; |
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} |
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static int ftsdc010_mmc_ofdata_to_platdata(struct udevice *dev) |
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{ |
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#if !CONFIG_IS_ENABLED(OF_PLATDATA) |
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struct ftsdc_priv *priv = dev_get_priv(dev); |
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struct ftsdc010_chip *chip = &priv->chip; |
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chip->name = dev->name; |
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chip->ioaddr = (void *)devfdt_get_addr(dev); |
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chip->buswidth = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev), |
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"bus-width", 4); |
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chip->priv = dev; |
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priv->fifo_depth = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev), |
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"fifo-depth", 0); |
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priv->fifo_mode = fdtdec_get_bool(gd->fdt_blob, dev_of_offset(dev), |
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"fifo-mode"); |
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if (fdtdec_get_int_array(gd->fdt_blob, dev_of_offset(dev), |
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"clock-freq-min-max", priv->minmax, 2)) { |
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int val = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev), |
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"max-frequency", -EINVAL); |
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if (val < 0) |
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return val; |
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priv->minmax[0] = 400000; /* 400 kHz */ |
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priv->minmax[1] = val; |
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} else { |
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debug("%s: 'clock-freq-min-max' property was deprecated.\n", |
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__func__); |
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} |
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#endif |
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chip->sclk = priv->minmax[1]; |
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chip->regs = chip->ioaddr; |
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return 0; |
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} |
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static int ftsdc010_mmc_probe(struct udevice *dev) |
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{ |
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struct ftsdc010_plat *plat = dev_get_platdata(dev); |
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struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev); |
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struct ftsdc_priv *priv = dev_get_priv(dev); |
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struct ftsdc010_chip *chip = &priv->chip; |
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struct udevice *pwr_dev __maybe_unused; |
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#if CONFIG_IS_ENABLED(OF_PLATDATA) |
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int ret; |
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struct ftsdc010 *dtplat = &plat->dtplat; |
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chip->name = dev->name; |
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chip->ioaddr = map_sysmem(dtplat->reg[0], dtplat->reg[1]); |
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chip->buswidth = dtplat->bus_width; |
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chip->priv = dev; |
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chip->dev_index = 1; |
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memcpy(priv->minmax, dtplat->clock_freq_min_max, sizeof(priv->minmax)); |
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ret = clk_get_by_index_platdata(dev, 0, dtplat->clocks, &priv->clk); |
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if (ret < 0) |
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return ret; |
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#endif |
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if (dev_read_bool(dev, "cap-mmc-highspeed") || \ |
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dev_read_bool(dev, "cap-sd-highspeed")) |
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chip->caps |= MMC_MODE_HS | MMC_MODE_HS_52MHz; |
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ftsdc_setup_cfg(&plat->cfg, dev->name, chip->buswidth, chip->caps, |
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priv->minmax[1] , priv->minmax[0]); |
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chip->mmc = &plat->mmc; |
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chip->mmc->priv = &priv->chip; |
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chip->mmc->dev = dev; |
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upriv->mmc = chip->mmc; |
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return ftsdc010_probe(dev); |
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} |
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int ftsdc010_mmc_bind(struct udevice *dev) |
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{ |
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struct ftsdc010_plat *plat = dev_get_platdata(dev); |
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return mmc_bind(dev, &plat->mmc, &plat->cfg); |
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} |
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static const struct udevice_id ftsdc010_mmc_ids[] = { |
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{ .compatible = "andestech,atfsdc010" }, |
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{ } |
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}; |
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U_BOOT_DRIVER(ftsdc010_mmc) = { |
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.name = "ftsdc010_mmc", |
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.id = UCLASS_MMC, |
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.of_match = ftsdc010_mmc_ids, |
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.ofdata_to_platdata = ftsdc010_mmc_ofdata_to_platdata, |
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.ops = &dm_ftsdc010_mmc_ops, |
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.bind = ftsdc010_mmc_bind, |
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.probe = ftsdc010_mmc_probe, |
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.priv_auto_alloc_size = sizeof(struct ftsdc_priv), |
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.platdata_auto_alloc_size = sizeof(struct ftsdc010_plat), |
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};
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