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806 lines
20 KiB
806 lines
20 KiB
// SPDX-License-Identifier: GPL-2.0 |
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/* |
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* bcm2835 sdhost driver. |
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* |
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* The 2835 has two SD controllers: The Arasan sdhci controller |
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* (supported by the iproc driver) and a custom sdhost controller |
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* (supported by this driver). |
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* |
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* The sdhci controller supports both sdcard and sdio. The sdhost |
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* controller supports the sdcard only, but has better performance. |
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* Also note that the rpi3 has sdio wifi, so driving the sdcard with |
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* the sdhost controller allows to use the sdhci controller for wifi |
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* support. |
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* |
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* The configuration is done by devicetree via pin muxing. Both |
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* SD controller are available on the same pins (2 pin groups = pin 22 |
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* to 27 + pin 48 to 53). So it's possible to use both SD controllers |
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* at the same time with different pin groups. |
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* |
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* This code was ported to U-Boot by |
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* Alexander Graf <[email protected]> |
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* and is based on drivers/mmc/host/bcm2835.c in Linux which is written by |
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* Phil Elwell <[email protected]> |
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* Copyright (C) 2015-2016 Raspberry Pi (Trading) Ltd. |
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* which is based on |
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* mmc-bcm2835.c by Gellert Weisz |
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* which is, in turn, based on |
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* sdhci-bcm2708.c by Broadcom |
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* sdhci-bcm2835.c by Stephen Warren and Oleksandr Tymoshenko |
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* sdhci.c and sdhci-pci.c by Pierre Ossman |
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*/ |
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#include <clk.h> |
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#include <common.h> |
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#include <dm.h> |
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#include <mmc.h> |
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#include <asm/arch/msg.h> |
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#include <asm/arch/mbox.h> |
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#include <asm/unaligned.h> |
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#include <linux/compat.h> |
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#include <linux/io.h> |
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#include <linux/iopoll.h> |
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#include <linux/sizes.h> |
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#include <mach/gpio.h> |
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#include <power/regulator.h> |
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|
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#define msleep(a) udelay(a * 1000) |
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|
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#define SDCMD 0x00 /* Command to SD card - 16 R/W */ |
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#define SDARG 0x04 /* Argument to SD card - 32 R/W */ |
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#define SDTOUT 0x08 /* Start value for timeout counter - 32 R/W */ |
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#define SDCDIV 0x0c /* Start value for clock divider - 11 R/W */ |
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#define SDRSP0 0x10 /* SD card response (31:0) - 32 R */ |
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#define SDRSP1 0x14 /* SD card response (63:32) - 32 R */ |
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#define SDRSP2 0x18 /* SD card response (95:64) - 32 R */ |
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#define SDRSP3 0x1c /* SD card response (127:96) - 32 R */ |
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#define SDHSTS 0x20 /* SD host status - 11 R/W */ |
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#define SDVDD 0x30 /* SD card power control - 1 R/W */ |
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#define SDEDM 0x34 /* Emergency Debug Mode - 13 R/W */ |
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#define SDHCFG 0x38 /* Host configuration - 2 R/W */ |
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#define SDHBCT 0x3c /* Host byte count (debug) - 32 R/W */ |
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#define SDDATA 0x40 /* Data to/from SD card - 32 R/W */ |
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#define SDHBLC 0x50 /* Host block count (SDIO/SDHC) - 9 R/W */ |
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|
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#define SDCMD_NEW_FLAG 0x8000 |
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#define SDCMD_FAIL_FLAG 0x4000 |
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#define SDCMD_BUSYWAIT 0x800 |
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#define SDCMD_NO_RESPONSE 0x400 |
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#define SDCMD_LONG_RESPONSE 0x200 |
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#define SDCMD_WRITE_CMD 0x80 |
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#define SDCMD_READ_CMD 0x40 |
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#define SDCMD_CMD_MASK 0x3f |
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|
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#define SDCDIV_MAX_CDIV 0x7ff |
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|
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#define SDHSTS_BUSY_IRPT 0x400 |
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#define SDHSTS_BLOCK_IRPT 0x200 |
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#define SDHSTS_SDIO_IRPT 0x100 |
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#define SDHSTS_REW_TIME_OUT 0x80 |
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#define SDHSTS_CMD_TIME_OUT 0x40 |
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#define SDHSTS_CRC16_ERROR 0x20 |
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#define SDHSTS_CRC7_ERROR 0x10 |
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#define SDHSTS_FIFO_ERROR 0x08 |
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#define SDHSTS_DATA_FLAG 0x01 |
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|
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#define SDHSTS_CLEAR_MASK (SDHSTS_BUSY_IRPT | \ |
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SDHSTS_BLOCK_IRPT | \ |
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SDHSTS_SDIO_IRPT | \ |
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SDHSTS_REW_TIME_OUT | \ |
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SDHSTS_CMD_TIME_OUT | \ |
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SDHSTS_CRC16_ERROR | \ |
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SDHSTS_CRC7_ERROR | \ |
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SDHSTS_FIFO_ERROR) |
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#define SDHSTS_TRANSFER_ERROR_MASK (SDHSTS_CRC7_ERROR | \ |
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SDHSTS_CRC16_ERROR | \ |
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SDHSTS_REW_TIME_OUT | \ |
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SDHSTS_FIFO_ERROR) |
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#define SDHSTS_ERROR_MASK (SDHSTS_CMD_TIME_OUT | \ |
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SDHSTS_TRANSFER_ERROR_MASK) |
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#define SDHCFG_BUSY_IRPT_EN BIT(10) |
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#define SDHCFG_BLOCK_IRPT_EN BIT(8) |
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#define SDHCFG_SDIO_IRPT_EN BIT(5) |
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#define SDHCFG_DATA_IRPT_EN BIT(4) |
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#define SDHCFG_SLOW_CARD BIT(3) |
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#define SDHCFG_WIDE_EXT_BUS BIT(2) |
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#define SDHCFG_WIDE_INT_BUS BIT(1) |
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#define SDHCFG_REL_CMD_LINE BIT(0) |
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#define SDVDD_POWER_OFF 0 |
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#define SDVDD_POWER_ON 1 |
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#define SDEDM_FORCE_DATA_MODE BIT(19) |
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#define SDEDM_CLOCK_PULSE BIT(20) |
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#define SDEDM_BYPASS BIT(21) |
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#define SDEDM_FIFO_FILL_SHIFT 4 |
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#define SDEDM_FIFO_FILL_MASK 0x1f |
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static u32 edm_fifo_fill(u32 edm) |
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{ |
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return (edm >> SDEDM_FIFO_FILL_SHIFT) & SDEDM_FIFO_FILL_MASK; |
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} |
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#define SDEDM_WRITE_THRESHOLD_SHIFT 9 |
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#define SDEDM_READ_THRESHOLD_SHIFT 14 |
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#define SDEDM_THRESHOLD_MASK 0x1f |
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#define SDEDM_FSM_MASK 0xf |
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#define SDEDM_FSM_IDENTMODE 0x0 |
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#define SDEDM_FSM_DATAMODE 0x1 |
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#define SDEDM_FSM_READDATA 0x2 |
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#define SDEDM_FSM_WRITEDATA 0x3 |
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#define SDEDM_FSM_READWAIT 0x4 |
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#define SDEDM_FSM_READCRC 0x5 |
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#define SDEDM_FSM_WRITECRC 0x6 |
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#define SDEDM_FSM_WRITEWAIT1 0x7 |
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#define SDEDM_FSM_POWERDOWN 0x8 |
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#define SDEDM_FSM_POWERUP 0x9 |
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#define SDEDM_FSM_WRITESTART1 0xa |
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#define SDEDM_FSM_WRITESTART2 0xb |
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#define SDEDM_FSM_GENPULSES 0xc |
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#define SDEDM_FSM_WRITEWAIT2 0xd |
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#define SDEDM_FSM_STARTPOWDOWN 0xf |
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#define SDDATA_FIFO_WORDS 16 |
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#define FIFO_READ_THRESHOLD 4 |
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#define FIFO_WRITE_THRESHOLD 4 |
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#define SDDATA_FIFO_PIO_BURST 8 |
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#define SDHST_TIMEOUT_MAX_USEC 100000 |
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struct bcm2835_plat { |
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struct mmc_config cfg; |
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struct mmc mmc; |
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}; |
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struct bcm2835_host { |
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void __iomem *ioaddr; |
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u32 phys_addr; |
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int clock; /* Current clock speed */ |
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unsigned int max_clk; /* Max possible freq */ |
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unsigned int blocks; /* remaining PIO blocks */ |
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u32 ns_per_fifo_word; |
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/* cached registers */ |
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u32 hcfg; |
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u32 cdiv; |
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struct mmc_cmd *cmd; /* Current command */ |
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struct mmc_data *data; /* Current data request */ |
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bool use_busy:1; /* Wait for busy interrupt */ |
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struct udevice *dev; |
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struct mmc *mmc; |
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struct bcm2835_plat *plat; |
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}; |
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static void bcm2835_dumpregs(struct bcm2835_host *host) |
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{ |
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dev_dbg(dev, "=========== REGISTER DUMP ===========\n"); |
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dev_dbg(dev, "SDCMD 0x%08x\n", readl(host->ioaddr + SDCMD)); |
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dev_dbg(dev, "SDARG 0x%08x\n", readl(host->ioaddr + SDARG)); |
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dev_dbg(dev, "SDTOUT 0x%08x\n", readl(host->ioaddr + SDTOUT)); |
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dev_dbg(dev, "SDCDIV 0x%08x\n", readl(host->ioaddr + SDCDIV)); |
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dev_dbg(dev, "SDRSP0 0x%08x\n", readl(host->ioaddr + SDRSP0)); |
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dev_dbg(dev, "SDRSP1 0x%08x\n", readl(host->ioaddr + SDRSP1)); |
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dev_dbg(dev, "SDRSP2 0x%08x\n", readl(host->ioaddr + SDRSP2)); |
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dev_dbg(dev, "SDRSP3 0x%08x\n", readl(host->ioaddr + SDRSP3)); |
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dev_dbg(dev, "SDHSTS 0x%08x\n", readl(host->ioaddr + SDHSTS)); |
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dev_dbg(dev, "SDVDD 0x%08x\n", readl(host->ioaddr + SDVDD)); |
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dev_dbg(dev, "SDEDM 0x%08x\n", readl(host->ioaddr + SDEDM)); |
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dev_dbg(dev, "SDHCFG 0x%08x\n", readl(host->ioaddr + SDHCFG)); |
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dev_dbg(dev, "SDHBCT 0x%08x\n", readl(host->ioaddr + SDHBCT)); |
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dev_dbg(dev, "SDHBLC 0x%08x\n", readl(host->ioaddr + SDHBLC)); |
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dev_dbg(dev, "===========================================\n"); |
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} |
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static void bcm2835_reset_internal(struct bcm2835_host *host) |
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{ |
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u32 temp; |
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writel(SDVDD_POWER_OFF, host->ioaddr + SDVDD); |
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writel(0, host->ioaddr + SDCMD); |
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writel(0, host->ioaddr + SDARG); |
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/* Set timeout to a big enough value so we don't hit it */ |
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writel(0xf00000, host->ioaddr + SDTOUT); |
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writel(0, host->ioaddr + SDCDIV); |
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/* Clear status register */ |
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writel(SDHSTS_CLEAR_MASK, host->ioaddr + SDHSTS); |
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writel(0, host->ioaddr + SDHCFG); |
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writel(0, host->ioaddr + SDHBCT); |
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writel(0, host->ioaddr + SDHBLC); |
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/* Limit fifo usage due to silicon bug */ |
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temp = readl(host->ioaddr + SDEDM); |
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temp &= ~((SDEDM_THRESHOLD_MASK << SDEDM_READ_THRESHOLD_SHIFT) | |
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(SDEDM_THRESHOLD_MASK << SDEDM_WRITE_THRESHOLD_SHIFT)); |
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temp |= (FIFO_READ_THRESHOLD << SDEDM_READ_THRESHOLD_SHIFT) | |
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(FIFO_WRITE_THRESHOLD << SDEDM_WRITE_THRESHOLD_SHIFT); |
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writel(temp, host->ioaddr + SDEDM); |
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/* Wait for FIFO threshold to populate */ |
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msleep(20); |
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writel(SDVDD_POWER_ON, host->ioaddr + SDVDD); |
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/* Wait for all components to go through power on cycle */ |
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msleep(20); |
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host->clock = 0; |
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writel(host->hcfg, host->ioaddr + SDHCFG); |
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writel(host->cdiv, host->ioaddr + SDCDIV); |
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} |
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static int bcm2835_wait_transfer_complete(struct bcm2835_host *host) |
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{ |
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int timediff = 0; |
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while (1) { |
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u32 edm, fsm; |
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edm = readl(host->ioaddr + SDEDM); |
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fsm = edm & SDEDM_FSM_MASK; |
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if ((fsm == SDEDM_FSM_IDENTMODE) || |
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(fsm == SDEDM_FSM_DATAMODE)) |
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break; |
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if ((fsm == SDEDM_FSM_READWAIT) || |
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(fsm == SDEDM_FSM_WRITESTART1) || |
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(fsm == SDEDM_FSM_READDATA)) { |
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writel(edm | SDEDM_FORCE_DATA_MODE, |
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host->ioaddr + SDEDM); |
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break; |
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} |
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/* Error out after 100000 register reads (~1s) */ |
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if (timediff++ == 100000) { |
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dev_err(host->dev, |
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"wait_transfer_complete - still waiting after %d retries\n", |
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timediff); |
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bcm2835_dumpregs(host); |
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return -ETIMEDOUT; |
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} |
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} |
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return 0; |
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} |
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static int bcm2835_transfer_block_pio(struct bcm2835_host *host, bool is_read) |
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{ |
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struct mmc_data *data = host->data; |
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size_t blksize = data->blocksize; |
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int copy_words; |
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u32 hsts = 0; |
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u32 *buf; |
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if (blksize % sizeof(u32)) |
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return -EINVAL; |
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buf = is_read ? (u32 *)data->dest : (u32 *)data->src; |
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if (is_read) |
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data->dest += blksize; |
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else |
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data->src += blksize; |
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copy_words = blksize / sizeof(u32); |
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/* |
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* Copy all contents from/to the FIFO as far as it reaches, |
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* then wait for it to fill/empty again and rewind. |
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*/ |
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while (copy_words) { |
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int burst_words, words; |
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u32 edm; |
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burst_words = min(SDDATA_FIFO_PIO_BURST, copy_words); |
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edm = readl(host->ioaddr + SDEDM); |
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if (is_read) |
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words = edm_fifo_fill(edm); |
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else |
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words = SDDATA_FIFO_WORDS - edm_fifo_fill(edm); |
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if (words < burst_words) { |
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int fsm_state = (edm & SDEDM_FSM_MASK); |
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if ((is_read && |
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(fsm_state != SDEDM_FSM_READDATA && |
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fsm_state != SDEDM_FSM_READWAIT && |
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fsm_state != SDEDM_FSM_READCRC)) || |
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(!is_read && |
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(fsm_state != SDEDM_FSM_WRITEDATA && |
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fsm_state != SDEDM_FSM_WRITEWAIT1 && |
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fsm_state != SDEDM_FSM_WRITEWAIT2 && |
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fsm_state != SDEDM_FSM_WRITECRC && |
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fsm_state != SDEDM_FSM_WRITESTART1 && |
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fsm_state != SDEDM_FSM_WRITESTART2))) { |
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hsts = readl(host->ioaddr + SDHSTS); |
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printf("fsm %x, hsts %08x\n", fsm_state, hsts); |
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if (hsts & SDHSTS_ERROR_MASK) |
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break; |
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} |
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continue; |
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} else if (words > copy_words) { |
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words = copy_words; |
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} |
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copy_words -= words; |
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/* Copy current chunk to/from the FIFO */ |
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while (words) { |
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if (is_read) |
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*(buf++) = readl(host->ioaddr + SDDATA); |
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else |
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writel(*(buf++), host->ioaddr + SDDATA); |
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words--; |
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} |
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} |
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return 0; |
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} |
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static int bcm2835_transfer_pio(struct bcm2835_host *host) |
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{ |
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u32 sdhsts; |
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bool is_read; |
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int ret = 0; |
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is_read = (host->data->flags & MMC_DATA_READ) != 0; |
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ret = bcm2835_transfer_block_pio(host, is_read); |
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if (ret) |
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return ret; |
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sdhsts = readl(host->ioaddr + SDHSTS); |
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if (sdhsts & (SDHSTS_CRC16_ERROR | |
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SDHSTS_CRC7_ERROR | |
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SDHSTS_FIFO_ERROR)) { |
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printf("%s transfer error - HSTS %08x\n", |
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is_read ? "read" : "write", sdhsts); |
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ret = -EILSEQ; |
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} else if ((sdhsts & (SDHSTS_CMD_TIME_OUT | |
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SDHSTS_REW_TIME_OUT))) { |
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printf("%s timeout error - HSTS %08x\n", |
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is_read ? "read" : "write", sdhsts); |
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ret = -ETIMEDOUT; |
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} |
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return ret; |
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} |
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static void bcm2835_prepare_data(struct bcm2835_host *host, struct mmc_cmd *cmd, |
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struct mmc_data *data) |
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{ |
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WARN_ON(host->data); |
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host->data = data; |
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if (!data) |
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return; |
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/* Use PIO */ |
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host->blocks = data->blocks; |
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writel(data->blocksize, host->ioaddr + SDHBCT); |
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writel(data->blocks, host->ioaddr + SDHBLC); |
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} |
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static u32 bcm2835_read_wait_sdcmd(struct bcm2835_host *host) |
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{ |
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u32 value; |
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int ret; |
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int timeout_us = SDHST_TIMEOUT_MAX_USEC; |
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ret = readl_poll_timeout(host->ioaddr + SDCMD, value, |
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!(value & SDCMD_NEW_FLAG), timeout_us); |
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if (ret == -ETIMEDOUT) |
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printf("%s: timeout (%d us)\n", __func__, timeout_us); |
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return value; |
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} |
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static int bcm2835_send_command(struct bcm2835_host *host, struct mmc_cmd *cmd, |
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struct mmc_data *data) |
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{ |
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u32 sdcmd, sdhsts; |
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WARN_ON(host->cmd); |
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if ((cmd->resp_type & MMC_RSP_136) && (cmd->resp_type & MMC_RSP_BUSY)) { |
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printf("unsupported response type!\n"); |
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return -EINVAL; |
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} |
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sdcmd = bcm2835_read_wait_sdcmd(host); |
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if (sdcmd & SDCMD_NEW_FLAG) { |
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printf("previous command never completed.\n"); |
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bcm2835_dumpregs(host); |
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return -EBUSY; |
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} |
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host->cmd = cmd; |
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/* Clear any error flags */ |
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sdhsts = readl(host->ioaddr + SDHSTS); |
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if (sdhsts & SDHSTS_ERROR_MASK) |
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writel(sdhsts, host->ioaddr + SDHSTS); |
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bcm2835_prepare_data(host, cmd, data); |
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writel(cmd->cmdarg, host->ioaddr + SDARG); |
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sdcmd = cmd->cmdidx & SDCMD_CMD_MASK; |
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host->use_busy = false; |
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if (!(cmd->resp_type & MMC_RSP_PRESENT)) { |
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sdcmd |= SDCMD_NO_RESPONSE; |
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} else { |
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if (cmd->resp_type & MMC_RSP_136) |
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sdcmd |= SDCMD_LONG_RESPONSE; |
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if (cmd->resp_type & MMC_RSP_BUSY) { |
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sdcmd |= SDCMD_BUSYWAIT; |
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host->use_busy = true; |
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} |
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} |
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if (data) { |
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if (data->flags & MMC_DATA_WRITE) |
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sdcmd |= SDCMD_WRITE_CMD; |
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if (data->flags & MMC_DATA_READ) |
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sdcmd |= SDCMD_READ_CMD; |
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} |
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writel(sdcmd | SDCMD_NEW_FLAG, host->ioaddr + SDCMD); |
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return 0; |
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} |
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static int bcm2835_finish_command(struct bcm2835_host *host) |
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{ |
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struct mmc_cmd *cmd = host->cmd; |
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u32 sdcmd; |
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int ret = 0; |
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sdcmd = bcm2835_read_wait_sdcmd(host); |
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/* Check for errors */ |
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if (sdcmd & SDCMD_NEW_FLAG) { |
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printf("command never completed.\n"); |
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bcm2835_dumpregs(host); |
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return -EIO; |
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} else if (sdcmd & SDCMD_FAIL_FLAG) { |
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u32 sdhsts = readl(host->ioaddr + SDHSTS); |
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/* Clear the errors */ |
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writel(SDHSTS_ERROR_MASK, host->ioaddr + SDHSTS); |
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if (!(sdhsts & SDHSTS_CRC7_ERROR) || |
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(host->cmd->cmdidx != MMC_CMD_SEND_OP_COND)) { |
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if (sdhsts & SDHSTS_CMD_TIME_OUT) { |
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ret = -ETIMEDOUT; |
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} else { |
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printf("unexpected command %d error\n", |
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host->cmd->cmdidx); |
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bcm2835_dumpregs(host); |
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ret = -EILSEQ; |
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} |
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return ret; |
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} |
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} |
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if (cmd->resp_type & MMC_RSP_PRESENT) { |
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if (cmd->resp_type & MMC_RSP_136) { |
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int i; |
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for (i = 0; i < 4; i++) { |
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cmd->response[3 - i] = |
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readl(host->ioaddr + SDRSP0 + i * 4); |
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} |
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} else { |
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cmd->response[0] = readl(host->ioaddr + SDRSP0); |
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} |
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} |
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/* Processed actual command. */ |
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host->cmd = NULL; |
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return ret; |
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} |
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static int bcm2835_check_cmd_error(struct bcm2835_host *host, u32 intmask) |
|
{ |
|
int ret = -EINVAL; |
|
|
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if (!(intmask & SDHSTS_ERROR_MASK)) |
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return 0; |
|
|
|
if (!host->cmd) |
|
return -EINVAL; |
|
|
|
printf("sdhost_busy_irq: intmask %08x\n", intmask); |
|
if (intmask & SDHSTS_CRC7_ERROR) { |
|
ret = -EILSEQ; |
|
} else if (intmask & (SDHSTS_CRC16_ERROR | |
|
SDHSTS_FIFO_ERROR)) { |
|
ret = -EILSEQ; |
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} else if (intmask & (SDHSTS_REW_TIME_OUT | SDHSTS_CMD_TIME_OUT)) { |
|
ret = -ETIMEDOUT; |
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} |
|
bcm2835_dumpregs(host); |
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return ret; |
|
} |
|
|
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static int bcm2835_check_data_error(struct bcm2835_host *host, u32 intmask) |
|
{ |
|
int ret = 0; |
|
|
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if (!host->data) |
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return 0; |
|
if (intmask & (SDHSTS_CRC16_ERROR | SDHSTS_FIFO_ERROR)) |
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ret = -EILSEQ; |
|
if (intmask & SDHSTS_REW_TIME_OUT) |
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ret = -ETIMEDOUT; |
|
|
|
if (ret) |
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printf("%s:%d %d\n", __func__, __LINE__, ret); |
|
|
|
return ret; |
|
} |
|
|
|
static int bcm2835_transmit(struct bcm2835_host *host) |
|
{ |
|
u32 intmask = readl(host->ioaddr + SDHSTS); |
|
int ret; |
|
|
|
/* Check for errors */ |
|
ret = bcm2835_check_data_error(host, intmask); |
|
if (ret) |
|
return ret; |
|
|
|
ret = bcm2835_check_cmd_error(host, intmask); |
|
if (ret) |
|
return ret; |
|
|
|
/* Handle wait for busy end */ |
|
if (host->use_busy && (intmask & SDHSTS_BUSY_IRPT)) { |
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writel(SDHSTS_BUSY_IRPT, host->ioaddr + SDHSTS); |
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host->use_busy = false; |
|
bcm2835_finish_command(host); |
|
} |
|
|
|
/* Handle PIO data transfer */ |
|
if (host->data) { |
|
ret = bcm2835_transfer_pio(host); |
|
if (ret) |
|
return ret; |
|
host->blocks--; |
|
if (host->blocks == 0) { |
|
/* Wait for command to complete for real */ |
|
ret = bcm2835_wait_transfer_complete(host); |
|
if (ret) |
|
return ret; |
|
/* Transfer complete */ |
|
host->data = NULL; |
|
} |
|
} |
|
|
|
return 0; |
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} |
|
|
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static void bcm2835_set_clock(struct bcm2835_host *host, unsigned int clock) |
|
{ |
|
int div; |
|
|
|
/* The SDCDIV register has 11 bits, and holds (div - 2). But |
|
* in data mode the max is 50MHz wihout a minimum, and only |
|
* the bottom 3 bits are used. Since the switch over is |
|
* automatic (unless we have marked the card as slow...), |
|
* chosen values have to make sense in both modes. Ident mode |
|
* must be 100-400KHz, so can range check the requested |
|
* clock. CMD15 must be used to return to data mode, so this |
|
* can be monitored. |
|
* |
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* clock 250MHz -> 0->125MHz, 1->83.3MHz, 2->62.5MHz, 3->50.0MHz |
|
* 4->41.7MHz, 5->35.7MHz, 6->31.3MHz, 7->27.8MHz |
|
* |
|
* 623->400KHz/27.8MHz |
|
* reset value (507)->491159/50MHz |
|
* |
|
* BUT, the 3-bit clock divisor in data mode is too small if |
|
* the core clock is higher than 250MHz, so instead use the |
|
* SLOW_CARD configuration bit to force the use of the ident |
|
* clock divisor at all times. |
|
*/ |
|
|
|
if (clock < 100000) { |
|
/* Can't stop the clock, but make it as slow as possible |
|
* to show willing |
|
*/ |
|
host->cdiv = SDCDIV_MAX_CDIV; |
|
writel(host->cdiv, host->ioaddr + SDCDIV); |
|
return; |
|
} |
|
|
|
div = host->max_clk / clock; |
|
if (div < 2) |
|
div = 2; |
|
if ((host->max_clk / div) > clock) |
|
div++; |
|
div -= 2; |
|
|
|
if (div > SDCDIV_MAX_CDIV) |
|
div = SDCDIV_MAX_CDIV; |
|
|
|
clock = host->max_clk / (div + 2); |
|
host->mmc->clock = clock; |
|
|
|
/* Calibrate some delays */ |
|
|
|
host->ns_per_fifo_word = (1000000000 / clock) * |
|
((host->mmc->card_caps & MMC_MODE_4BIT) ? 8 : 32); |
|
|
|
host->cdiv = div; |
|
writel(host->cdiv, host->ioaddr + SDCDIV); |
|
|
|
/* Set the timeout to 500ms */ |
|
writel(host->mmc->clock / 2, host->ioaddr + SDTOUT); |
|
} |
|
|
|
static inline int is_power_of_2(u64 x) |
|
{ |
|
return !(x & (x - 1)); |
|
} |
|
|
|
static int bcm2835_send_cmd(struct udevice *dev, struct mmc_cmd *cmd, |
|
struct mmc_data *data) |
|
{ |
|
struct bcm2835_host *host = dev_get_priv(dev); |
|
u32 edm, fsm; |
|
int ret = 0; |
|
|
|
if (data && !is_power_of_2(data->blocksize)) { |
|
printf("unsupported block size (%d bytes)\n", data->blocksize); |
|
|
|
if (cmd) |
|
return -EINVAL; |
|
} |
|
|
|
edm = readl(host->ioaddr + SDEDM); |
|
fsm = edm & SDEDM_FSM_MASK; |
|
|
|
if ((fsm != SDEDM_FSM_IDENTMODE) && |
|
(fsm != SDEDM_FSM_DATAMODE) && |
|
(cmd && cmd->cmdidx != MMC_CMD_STOP_TRANSMISSION)) { |
|
printf("previous command (%d) not complete (EDM %08x)\n", |
|
readl(host->ioaddr + SDCMD) & SDCMD_CMD_MASK, edm); |
|
bcm2835_dumpregs(host); |
|
|
|
if (cmd) |
|
return -EILSEQ; |
|
|
|
return 0; |
|
} |
|
|
|
if (cmd) { |
|
ret = bcm2835_send_command(host, cmd, data); |
|
if (!ret && !host->use_busy) |
|
ret = bcm2835_finish_command(host); |
|
} |
|
|
|
/* Wait for completion of busy signal or data transfer */ |
|
while (host->use_busy || host->data) { |
|
ret = bcm2835_transmit(host); |
|
if (ret) |
|
break; |
|
} |
|
|
|
return ret; |
|
} |
|
|
|
static int bcm2835_set_ios(struct udevice *dev) |
|
{ |
|
struct bcm2835_host *host = dev_get_priv(dev); |
|
struct mmc *mmc = mmc_get_mmc_dev(dev); |
|
|
|
if (!mmc->clock || mmc->clock != host->clock) { |
|
bcm2835_set_clock(host, mmc->clock); |
|
host->clock = mmc->clock; |
|
} |
|
|
|
/* set bus width */ |
|
host->hcfg &= ~SDHCFG_WIDE_EXT_BUS; |
|
if (mmc->bus_width == 4) |
|
host->hcfg |= SDHCFG_WIDE_EXT_BUS; |
|
|
|
host->hcfg |= SDHCFG_WIDE_INT_BUS; |
|
|
|
/* Disable clever clock switching, to cope with fast core clocks */ |
|
host->hcfg |= SDHCFG_SLOW_CARD; |
|
|
|
writel(host->hcfg, host->ioaddr + SDHCFG); |
|
|
|
return 0; |
|
} |
|
|
|
static void bcm2835_add_host(struct bcm2835_host *host) |
|
{ |
|
struct mmc_config *cfg = &host->plat->cfg; |
|
|
|
cfg->f_max = host->max_clk; |
|
cfg->f_min = host->max_clk / SDCDIV_MAX_CDIV; |
|
cfg->b_max = 65535; |
|
|
|
dev_dbg(dev, "f_max %d, f_min %d\n", |
|
cfg->f_max, cfg->f_min); |
|
|
|
/* host controller capabilities */ |
|
cfg->host_caps = MMC_MODE_4BIT | MMC_MODE_HS | MMC_MODE_HS_52MHz; |
|
|
|
/* report supported voltage ranges */ |
|
cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34; |
|
|
|
/* Set interrupt enables */ |
|
host->hcfg = SDHCFG_BUSY_IRPT_EN; |
|
|
|
bcm2835_reset_internal(host); |
|
} |
|
|
|
static int bcm2835_probe(struct udevice *dev) |
|
{ |
|
struct bcm2835_plat *plat = dev_get_platdata(dev); |
|
struct bcm2835_host *host = dev_get_priv(dev); |
|
struct mmc *mmc = mmc_get_mmc_dev(dev); |
|
struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev); |
|
|
|
host->dev = dev; |
|
host->mmc = mmc; |
|
host->plat = plat; |
|
upriv->mmc = &plat->mmc; |
|
plat->cfg.name = dev->name; |
|
|
|
host->phys_addr = devfdt_get_addr(dev); |
|
if (host->phys_addr == FDT_ADDR_T_NONE) |
|
return -EINVAL; |
|
|
|
host->ioaddr = devm_ioremap(dev, host->phys_addr, SZ_256); |
|
if (!host->ioaddr) |
|
return -ENOMEM; |
|
|
|
host->max_clk = bcm2835_get_mmc_clock(BCM2835_MBOX_CLOCK_ID_CORE); |
|
|
|
bcm2835_add_host(host); |
|
|
|
dev_dbg(dev, "%s -> OK\n", __func__); |
|
|
|
return 0; |
|
} |
|
|
|
static const struct udevice_id bcm2835_match[] = { |
|
{ .compatible = "brcm,bcm2835-sdhost" }, |
|
{ } |
|
}; |
|
|
|
static const struct dm_mmc_ops bcm2835_ops = { |
|
.send_cmd = bcm2835_send_cmd, |
|
.set_ios = bcm2835_set_ios, |
|
}; |
|
|
|
static int bcm2835_bind(struct udevice *dev) |
|
{ |
|
struct bcm2835_plat *plat = dev_get_platdata(dev); |
|
|
|
return mmc_bind(dev, &plat->mmc, &plat->cfg); |
|
} |
|
|
|
U_BOOT_DRIVER(bcm2835_sdhost) = { |
|
.name = "bcm2835-sdhost", |
|
.id = UCLASS_MMC, |
|
.of_match = bcm2835_match, |
|
.bind = bcm2835_bind, |
|
.probe = bcm2835_probe, |
|
.priv_auto_alloc_size = sizeof(struct bcm2835_host), |
|
.platdata_auto_alloc_size = sizeof(struct bcm2835_plat), |
|
.ops = &bcm2835_ops, |
|
};
|
|
|