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313 lines
8.9 KiB
313 lines
8.9 KiB
// SPDX-License-Identifier: GPL-2.0+ |
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/* |
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* Driver for the Zynq-7000 PS I2C controller |
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* IP from Cadence (ID T-CS-PE-0007-100, Version R1p10f2) |
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* |
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* Author: Joe Hershberger <[email protected]> |
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* Copyright (c) 2012 Joe Hershberger. |
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* |
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* Copyright (c) 2012-2013 Xilinx, Michal Simek |
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* |
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* NOTE: This driver should be converted to driver model before June 2017. |
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* Please see doc/driver-model/i2c-howto.txt for instructions. |
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*/ |
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#include <common.h> |
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#include <asm/io.h> |
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#include <i2c.h> |
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#include <linux/errno.h> |
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#include <asm/arch/hardware.h> |
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/* i2c register set */ |
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struct zynq_i2c_registers { |
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u32 control; |
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u32 status; |
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u32 address; |
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u32 data; |
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u32 interrupt_status; |
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u32 transfer_size; |
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u32 slave_mon_pause; |
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u32 time_out; |
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u32 interrupt_mask; |
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u32 interrupt_enable; |
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u32 interrupt_disable; |
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}; |
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/* Control register fields */ |
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#define ZYNQ_I2C_CONTROL_RW 0x00000001 |
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#define ZYNQ_I2C_CONTROL_MS 0x00000002 |
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#define ZYNQ_I2C_CONTROL_NEA 0x00000004 |
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#define ZYNQ_I2C_CONTROL_ACKEN 0x00000008 |
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#define ZYNQ_I2C_CONTROL_HOLD 0x00000010 |
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#define ZYNQ_I2C_CONTROL_SLVMON 0x00000020 |
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#define ZYNQ_I2C_CONTROL_CLR_FIFO 0x00000040 |
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#define ZYNQ_I2C_CONTROL_DIV_B_SHIFT 8 |
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#define ZYNQ_I2C_CONTROL_DIV_B_MASK 0x00003F00 |
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#define ZYNQ_I2C_CONTROL_DIV_A_SHIFT 14 |
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#define ZYNQ_I2C_CONTROL_DIV_A_MASK 0x0000C000 |
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/* Status register values */ |
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#define ZYNQ_I2C_STATUS_RXDV 0x00000020 |
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#define ZYNQ_I2C_STATUS_TXDV 0x00000040 |
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#define ZYNQ_I2C_STATUS_RXOVF 0x00000080 |
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#define ZYNQ_I2C_STATUS_BA 0x00000100 |
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/* Interrupt register fields */ |
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#define ZYNQ_I2C_INTERRUPT_COMP 0x00000001 |
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#define ZYNQ_I2C_INTERRUPT_DATA 0x00000002 |
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#define ZYNQ_I2C_INTERRUPT_NACK 0x00000004 |
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#define ZYNQ_I2C_INTERRUPT_TO 0x00000008 |
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#define ZYNQ_I2C_INTERRUPT_SLVRDY 0x00000010 |
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#define ZYNQ_I2C_INTERRUPT_RXOVF 0x00000020 |
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#define ZYNQ_I2C_INTERRUPT_TXOVF 0x00000040 |
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#define ZYNQ_I2C_INTERRUPT_RXUNF 0x00000080 |
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#define ZYNQ_I2C_INTERRUPT_ARBLOST 0x00000200 |
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#define ZYNQ_I2C_FIFO_DEPTH 16 |
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#define ZYNQ_I2C_TRANSFERT_SIZE_MAX 255 /* Controller transfer limit */ |
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static struct zynq_i2c_registers *i2c_select(struct i2c_adapter *adap) |
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{ |
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return adap->hwadapnr ? |
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/* Zynq PS I2C1 */ |
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(struct zynq_i2c_registers *)ZYNQ_I2C_BASEADDR1 : |
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/* Zynq PS I2C0 */ |
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(struct zynq_i2c_registers *)ZYNQ_I2C_BASEADDR0; |
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} |
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/* I2C init called by cmd_i2c when doing 'i2c reset'. */ |
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static void zynq_i2c_init(struct i2c_adapter *adap, int requested_speed, |
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int slaveadd) |
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{ |
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struct zynq_i2c_registers *zynq_i2c = i2c_select(adap); |
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/* 111MHz / ( (3 * 17) * 22 ) = ~100KHz */ |
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writel((16 << ZYNQ_I2C_CONTROL_DIV_B_SHIFT) | |
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(2 << ZYNQ_I2C_CONTROL_DIV_A_SHIFT), &zynq_i2c->control); |
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/* Enable master mode, ack, and 7-bit addressing */ |
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setbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_MS | |
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ZYNQ_I2C_CONTROL_ACKEN | ZYNQ_I2C_CONTROL_NEA); |
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} |
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#ifdef DEBUG |
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static void zynq_i2c_debug_status(struct zynq_i2c_registers *zynq_i2c) |
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{ |
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int int_status; |
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int status; |
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int_status = readl(&zynq_i2c->interrupt_status); |
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status = readl(&zynq_i2c->status); |
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if (int_status || status) { |
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debug("Status: "); |
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if (int_status & ZYNQ_I2C_INTERRUPT_COMP) |
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debug("COMP "); |
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if (int_status & ZYNQ_I2C_INTERRUPT_DATA) |
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debug("DATA "); |
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if (int_status & ZYNQ_I2C_INTERRUPT_NACK) |
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debug("NACK "); |
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if (int_status & ZYNQ_I2C_INTERRUPT_TO) |
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debug("TO "); |
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if (int_status & ZYNQ_I2C_INTERRUPT_SLVRDY) |
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debug("SLVRDY "); |
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if (int_status & ZYNQ_I2C_INTERRUPT_RXOVF) |
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debug("RXOVF "); |
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if (int_status & ZYNQ_I2C_INTERRUPT_TXOVF) |
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debug("TXOVF "); |
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if (int_status & ZYNQ_I2C_INTERRUPT_RXUNF) |
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debug("RXUNF "); |
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if (int_status & ZYNQ_I2C_INTERRUPT_ARBLOST) |
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debug("ARBLOST "); |
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if (status & ZYNQ_I2C_STATUS_RXDV) |
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debug("RXDV "); |
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if (status & ZYNQ_I2C_STATUS_TXDV) |
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debug("TXDV "); |
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if (status & ZYNQ_I2C_STATUS_RXOVF) |
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debug("RXOVF "); |
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if (status & ZYNQ_I2C_STATUS_BA) |
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debug("BA "); |
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debug("TS%d ", readl(&zynq_i2c->transfer_size)); |
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debug("\n"); |
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} |
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} |
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#endif |
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/* Wait for an interrupt */ |
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static u32 zynq_i2c_wait(struct zynq_i2c_registers *zynq_i2c, u32 mask) |
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{ |
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int timeout, int_status; |
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for (timeout = 0; timeout < 100; timeout++) { |
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udelay(100); |
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int_status = readl(&zynq_i2c->interrupt_status); |
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if (int_status & mask) |
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break; |
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} |
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#ifdef DEBUG |
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zynq_i2c_debug_status(zynq_i2c); |
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#endif |
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/* Clear interrupt status flags */ |
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writel(int_status & mask, &zynq_i2c->interrupt_status); |
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return int_status & mask; |
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} |
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/* |
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* I2C probe called by cmd_i2c when doing 'i2c probe'. |
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* Begin read, nak data byte, end. |
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*/ |
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static int zynq_i2c_probe(struct i2c_adapter *adap, u8 dev) |
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{ |
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struct zynq_i2c_registers *zynq_i2c = i2c_select(adap); |
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/* Attempt to read a byte */ |
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setbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_CLR_FIFO | |
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ZYNQ_I2C_CONTROL_RW); |
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clrbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_HOLD); |
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writel(0xFF, &zynq_i2c->interrupt_status); |
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writel(dev, &zynq_i2c->address); |
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writel(1, &zynq_i2c->transfer_size); |
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return (zynq_i2c_wait(zynq_i2c, ZYNQ_I2C_INTERRUPT_COMP | |
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ZYNQ_I2C_INTERRUPT_NACK) & |
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ZYNQ_I2C_INTERRUPT_COMP) ? 0 : -ETIMEDOUT; |
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} |
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/* |
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* I2C read called by cmd_i2c when doing 'i2c read' and by cmd_eeprom.c |
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* Begin write, send address byte(s), begin read, receive data bytes, end. |
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*/ |
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static int zynq_i2c_read(struct i2c_adapter *adap, u8 dev, uint addr, |
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int alen, u8 *data, int length) |
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{ |
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u32 status; |
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u32 i = 0; |
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u8 *cur_data = data; |
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struct zynq_i2c_registers *zynq_i2c = i2c_select(adap); |
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/* Check the hardware can handle the requested bytes */ |
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if ((length < 0) || (length > ZYNQ_I2C_TRANSFERT_SIZE_MAX)) |
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return -EINVAL; |
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/* Write the register address */ |
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setbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_CLR_FIFO | |
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ZYNQ_I2C_CONTROL_HOLD); |
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/* |
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* Temporarily disable restart (by clearing hold) |
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* It doesn't seem to work. |
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*/ |
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clrbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_HOLD); |
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writel(0xFF, &zynq_i2c->interrupt_status); |
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if (alen) { |
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clrbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_RW); |
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writel(dev, &zynq_i2c->address); |
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while (alen--) |
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writel(addr >> (8 * alen), &zynq_i2c->data); |
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/* Wait for the address to be sent */ |
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if (!zynq_i2c_wait(zynq_i2c, ZYNQ_I2C_INTERRUPT_COMP)) { |
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/* Release the bus */ |
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clrbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_HOLD); |
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return -ETIMEDOUT; |
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} |
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debug("Device acked address\n"); |
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} |
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setbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_CLR_FIFO | |
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ZYNQ_I2C_CONTROL_RW); |
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/* Start reading data */ |
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writel(dev, &zynq_i2c->address); |
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writel(length, &zynq_i2c->transfer_size); |
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/* Wait for data */ |
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do { |
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status = zynq_i2c_wait(zynq_i2c, ZYNQ_I2C_INTERRUPT_COMP | |
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ZYNQ_I2C_INTERRUPT_DATA); |
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if (!status) { |
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/* Release the bus */ |
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clrbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_HOLD); |
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return -ETIMEDOUT; |
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} |
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debug("Read %d bytes\n", |
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length - readl(&zynq_i2c->transfer_size)); |
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for (; i < length - readl(&zynq_i2c->transfer_size); i++) |
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*(cur_data++) = readl(&zynq_i2c->data); |
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} while (readl(&zynq_i2c->transfer_size) != 0); |
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/* All done... release the bus */ |
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clrbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_HOLD); |
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#ifdef DEBUG |
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zynq_i2c_debug_status(zynq_i2c); |
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#endif |
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return 0; |
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} |
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/* |
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* I2C write called by cmd_i2c when doing 'i2c write' and by cmd_eeprom.c |
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* Begin write, send address byte(s), send data bytes, end. |
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*/ |
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static int zynq_i2c_write(struct i2c_adapter *adap, u8 dev, uint addr, |
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int alen, u8 *data, int length) |
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{ |
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u8 *cur_data = data; |
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struct zynq_i2c_registers *zynq_i2c = i2c_select(adap); |
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/* Write the register address */ |
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setbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_CLR_FIFO | |
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ZYNQ_I2C_CONTROL_HOLD); |
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clrbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_RW); |
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writel(0xFF, &zynq_i2c->interrupt_status); |
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writel(dev, &zynq_i2c->address); |
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if (alen) { |
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while (alen--) |
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writel(addr >> (8 * alen), &zynq_i2c->data); |
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/* Start the tranfer */ |
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if (!zynq_i2c_wait(zynq_i2c, ZYNQ_I2C_INTERRUPT_COMP)) { |
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/* Release the bus */ |
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clrbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_HOLD); |
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return -ETIMEDOUT; |
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} |
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debug("Device acked address\n"); |
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} |
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while (length--) { |
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writel(*(cur_data++), &zynq_i2c->data); |
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if (readl(&zynq_i2c->transfer_size) == ZYNQ_I2C_FIFO_DEPTH) { |
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if (!zynq_i2c_wait(zynq_i2c, ZYNQ_I2C_INTERRUPT_COMP)) { |
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/* Release the bus */ |
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clrbits_le32(&zynq_i2c->control, |
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ZYNQ_I2C_CONTROL_HOLD); |
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return -ETIMEDOUT; |
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} |
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} |
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} |
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/* All done... release the bus */ |
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clrbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_HOLD); |
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/* Wait for the address and data to be sent */ |
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if (!zynq_i2c_wait(zynq_i2c, ZYNQ_I2C_INTERRUPT_COMP)) |
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return -ETIMEDOUT; |
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return 0; |
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} |
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static unsigned int zynq_i2c_set_bus_speed(struct i2c_adapter *adap, |
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unsigned int speed) |
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{ |
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if (speed != 1000000) |
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return -EINVAL; |
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return 0; |
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} |
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#ifdef CONFIG_ZYNQ_I2C0 |
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U_BOOT_I2C_ADAP_COMPLETE(zynq_0, zynq_i2c_init, zynq_i2c_probe, zynq_i2c_read, |
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zynq_i2c_write, zynq_i2c_set_bus_speed, |
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CONFIG_SYS_I2C_ZYNQ_SPEED, CONFIG_SYS_I2C_ZYNQ_SLAVE, |
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0) |
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#endif |
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#ifdef CONFIG_ZYNQ_I2C1 |
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U_BOOT_I2C_ADAP_COMPLETE(zynq_1, zynq_i2c_init, zynq_i2c_probe, zynq_i2c_read, |
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zynq_i2c_write, zynq_i2c_set_bus_speed, |
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CONFIG_SYS_I2C_ZYNQ_SPEED, CONFIG_SYS_I2C_ZYNQ_SLAVE, |
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1) |
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#endif
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