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310 lines
7.1 KiB
310 lines
7.1 KiB
// SPDX-License-Identifier: GPL-2.0+ |
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/* |
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* Copyright (C) 2011, 2013 Renesas Solutions Corp. |
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* Copyright (C) 2011, 2013 Nobuhiro Iwamatsu <[email protected]> |
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* |
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* NOTE: This driver should be converted to driver model before June 2017. |
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* Please see doc/driver-model/i2c-howto.txt for instructions. |
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*/ |
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#include <common.h> |
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#include <i2c.h> |
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#include <asm/io.h> |
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DECLARE_GLOBAL_DATA_PTR; |
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/* Every register is 32bit aligned, but only 8bits in size */ |
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#define ureg(name) u8 name; u8 __pad_##name##0; u16 __pad_##name##1; |
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struct sh_i2c { |
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ureg(icdr); |
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ureg(iccr); |
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ureg(icsr); |
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ureg(icic); |
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ureg(iccl); |
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ureg(icch); |
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}; |
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#undef ureg |
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/* ICCR */ |
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#define SH_I2C_ICCR_ICE (1 << 7) |
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#define SH_I2C_ICCR_RACK (1 << 6) |
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#define SH_I2C_ICCR_RTS (1 << 4) |
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#define SH_I2C_ICCR_BUSY (1 << 2) |
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#define SH_I2C_ICCR_SCP (1 << 0) |
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/* ICSR / ICIC */ |
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#define SH_IC_BUSY (1 << 4) |
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#define SH_IC_TACK (1 << 2) |
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#define SH_IC_WAIT (1 << 1) |
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#define SH_IC_DTE (1 << 0) |
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#ifdef CONFIG_SH_I2C_8BIT |
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/* store 8th bit of iccl and icch in ICIC register */ |
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#define SH_I2C_ICIC_ICCLB8 (1 << 7) |
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#define SH_I2C_ICIC_ICCHB8 (1 << 6) |
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#endif |
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static const struct sh_i2c *i2c_dev[CONFIG_SYS_I2C_SH_NUM_CONTROLLERS] = { |
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(struct sh_i2c *)CONFIG_SYS_I2C_SH_BASE0, |
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#ifdef CONFIG_SYS_I2C_SH_BASE1 |
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(struct sh_i2c *)CONFIG_SYS_I2C_SH_BASE1, |
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#endif |
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#ifdef CONFIG_SYS_I2C_SH_BASE2 |
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(struct sh_i2c *)CONFIG_SYS_I2C_SH_BASE2, |
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#endif |
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#ifdef CONFIG_SYS_I2C_SH_BASE3 |
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(struct sh_i2c *)CONFIG_SYS_I2C_SH_BASE3, |
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#endif |
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#ifdef CONFIG_SYS_I2C_SH_BASE4 |
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(struct sh_i2c *)CONFIG_SYS_I2C_SH_BASE4, |
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#endif |
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}; |
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static u16 iccl, icch; |
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#define IRQ_WAIT 1000 |
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static void sh_irq_dte(struct sh_i2c *dev) |
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{ |
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int i; |
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for (i = 0; i < IRQ_WAIT; i++) { |
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if (SH_IC_DTE & readb(&dev->icsr)) |
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break; |
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udelay(10); |
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} |
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} |
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static int sh_irq_dte_with_tack(struct sh_i2c *dev) |
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{ |
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int i; |
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for (i = 0; i < IRQ_WAIT; i++) { |
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if (SH_IC_DTE & readb(&dev->icsr)) |
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break; |
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if (SH_IC_TACK & readb(&dev->icsr)) |
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return -1; |
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udelay(10); |
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} |
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return 0; |
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} |
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static void sh_irq_busy(struct sh_i2c *dev) |
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{ |
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int i; |
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for (i = 0; i < IRQ_WAIT; i++) { |
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if (!(SH_IC_BUSY & readb(&dev->icsr))) |
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break; |
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udelay(10); |
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} |
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} |
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static int sh_i2c_set_addr(struct sh_i2c *dev, u8 chip, u8 addr, int stop) |
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{ |
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u8 icic = SH_IC_TACK; |
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debug("%s: chip: %x, addr: %x iccl: %x, icch %x\n", |
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__func__, chip, addr, iccl, icch); |
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clrbits_8(&dev->iccr, SH_I2C_ICCR_ICE); |
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setbits_8(&dev->iccr, SH_I2C_ICCR_ICE); |
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writeb(iccl & 0xff, &dev->iccl); |
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writeb(icch & 0xff, &dev->icch); |
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#ifdef CONFIG_SH_I2C_8BIT |
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if (iccl > 0xff) |
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icic |= SH_I2C_ICIC_ICCLB8; |
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if (icch > 0xff) |
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icic |= SH_I2C_ICIC_ICCHB8; |
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#endif |
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writeb(icic, &dev->icic); |
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writeb((SH_I2C_ICCR_ICE|SH_I2C_ICCR_RTS|SH_I2C_ICCR_BUSY), &dev->iccr); |
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sh_irq_dte(dev); |
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clrbits_8(&dev->icsr, SH_IC_TACK); |
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writeb(chip << 1, &dev->icdr); |
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if (sh_irq_dte_with_tack(dev) != 0) |
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return -1; |
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writeb(addr, &dev->icdr); |
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if (stop) |
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writeb((SH_I2C_ICCR_ICE|SH_I2C_ICCR_RTS), &dev->iccr); |
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if (sh_irq_dte_with_tack(dev) != 0) |
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return -1; |
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return 0; |
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} |
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static void sh_i2c_finish(struct sh_i2c *dev) |
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{ |
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writeb(0, &dev->icsr); |
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clrbits_8(&dev->iccr, SH_I2C_ICCR_ICE); |
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} |
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static int |
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sh_i2c_raw_write(struct sh_i2c *dev, u8 chip, uint addr, u8 val) |
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{ |
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int ret = -1; |
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if (sh_i2c_set_addr(dev, chip, addr, 0) != 0) |
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goto exit0; |
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udelay(10); |
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writeb(val, &dev->icdr); |
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if (sh_irq_dte_with_tack(dev) != 0) |
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goto exit0; |
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writeb((SH_I2C_ICCR_ICE | SH_I2C_ICCR_RTS), &dev->iccr); |
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if (sh_irq_dte_with_tack(dev) != 0) |
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goto exit0; |
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sh_irq_busy(dev); |
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ret = 0; |
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exit0: |
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sh_i2c_finish(dev); |
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return ret; |
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} |
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static int sh_i2c_raw_read(struct sh_i2c *dev, u8 chip, u8 addr) |
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{ |
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int ret = -1; |
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#if defined(CONFIG_SH73A0) |
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if (sh_i2c_set_addr(dev, chip, addr, 0) != 0) |
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goto exit0; |
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#else |
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if (sh_i2c_set_addr(dev, chip, addr, 1) != 0) |
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goto exit0; |
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udelay(100); |
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#endif |
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writeb((SH_I2C_ICCR_ICE|SH_I2C_ICCR_RTS|SH_I2C_ICCR_BUSY), &dev->iccr); |
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sh_irq_dte(dev); |
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writeb(chip << 1 | 0x01, &dev->icdr); |
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if (sh_irq_dte_with_tack(dev) != 0) |
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goto exit0; |
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writeb((SH_I2C_ICCR_ICE|SH_I2C_ICCR_SCP), &dev->iccr); |
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if (sh_irq_dte_with_tack(dev) != 0) |
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goto exit0; |
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ret = readb(&dev->icdr) & 0xff; |
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writeb((SH_I2C_ICCR_ICE|SH_I2C_ICCR_RACK), &dev->iccr); |
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readb(&dev->icdr); /* Dummy read */ |
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sh_irq_busy(dev); |
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exit0: |
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sh_i2c_finish(dev); |
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return ret; |
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} |
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static void |
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sh_i2c_init(struct i2c_adapter *adap, int speed, int slaveadd) |
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{ |
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int num, denom, tmp; |
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/* No i2c support prior to relocation */ |
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if (!(gd->flags & GD_FLG_RELOC)) |
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return; |
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/* |
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* Calculate the value for iccl. From the data sheet: |
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* iccl = (p-clock / transfer-rate) * (L / (L + H)) |
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* where L and H are the SCL low and high ratio. |
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*/ |
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num = CONFIG_SH_I2C_CLOCK * CONFIG_SH_I2C_DATA_LOW; |
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denom = speed * (CONFIG_SH_I2C_DATA_HIGH + CONFIG_SH_I2C_DATA_LOW); |
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tmp = num * 10 / denom; |
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if (tmp % 10 >= 5) |
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iccl = (u16)((num/denom) + 1); |
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else |
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iccl = (u16)(num/denom); |
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/* Calculate the value for icch. From the data sheet: |
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icch = (p clock / transfer rate) * (H / (L + H)) */ |
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num = CONFIG_SH_I2C_CLOCK * CONFIG_SH_I2C_DATA_HIGH; |
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tmp = num * 10 / denom; |
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if (tmp % 10 >= 5) |
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icch = (u16)((num/denom) + 1); |
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else |
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icch = (u16)(num/denom); |
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debug("clock: %d, speed %d, iccl: %x, icch: %x\n", |
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CONFIG_SH_I2C_CLOCK, speed, iccl, icch); |
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} |
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static int sh_i2c_read(struct i2c_adapter *adap, uint8_t chip, |
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uint addr, int alen, u8 *data, int len) |
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{ |
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int ret, i; |
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struct sh_i2c *dev = (struct sh_i2c *)i2c_dev[adap->hwadapnr]; |
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for (i = 0; i < len; i++) { |
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ret = sh_i2c_raw_read(dev, chip, addr + i); |
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if (ret < 0) |
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return -1; |
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data[i] = ret & 0xff; |
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debug("%s: data[%d]: %02x\n", __func__, i, data[i]); |
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} |
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return 0; |
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} |
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static int sh_i2c_write(struct i2c_adapter *adap, uint8_t chip, uint addr, |
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int alen, u8 *data, int len) |
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{ |
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struct sh_i2c *dev = (struct sh_i2c *)i2c_dev[adap->hwadapnr]; |
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int i; |
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for (i = 0; i < len; i++) { |
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debug("%s: data[%d]: %02x\n", __func__, i, data[i]); |
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if (sh_i2c_raw_write(dev, chip, addr + i, data[i]) != 0) |
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return -1; |
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} |
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return 0; |
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} |
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static int |
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sh_i2c_probe(struct i2c_adapter *adap, u8 dev) |
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{ |
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u8 dummy[1]; |
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return sh_i2c_read(adap, dev, 0, 0, dummy, sizeof dummy); |
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} |
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static unsigned int sh_i2c_set_bus_speed(struct i2c_adapter *adap, |
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unsigned int speed) |
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{ |
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struct sh_i2c *dev = (struct sh_i2c *)i2c_dev[adap->hwadapnr]; |
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sh_i2c_finish(dev); |
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sh_i2c_init(adap, speed, 0); |
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return 0; |
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} |
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/* |
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* Register RCAR i2c adapters |
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*/ |
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U_BOOT_I2C_ADAP_COMPLETE(sh_0, sh_i2c_init, sh_i2c_probe, sh_i2c_read, |
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sh_i2c_write, sh_i2c_set_bus_speed, CONFIG_SYS_I2C_SH_SPEED0, 0, 0) |
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#ifdef CONFIG_SYS_I2C_SH_BASE1 |
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U_BOOT_I2C_ADAP_COMPLETE(sh_1, sh_i2c_init, sh_i2c_probe, sh_i2c_read, |
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sh_i2c_write, sh_i2c_set_bus_speed, CONFIG_SYS_I2C_SH_SPEED1, 0, 1) |
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#endif |
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#ifdef CONFIG_SYS_I2C_SH_BASE2 |
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U_BOOT_I2C_ADAP_COMPLETE(sh_2, sh_i2c_init, sh_i2c_probe, sh_i2c_read, |
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sh_i2c_write, sh_i2c_set_bus_speed, CONFIG_SYS_I2C_SH_SPEED2, 0, 2) |
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#endif |
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#ifdef CONFIG_SYS_I2C_SH_BASE3 |
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U_BOOT_I2C_ADAP_COMPLETE(sh_3, sh_i2c_init, sh_i2c_probe, sh_i2c_read, |
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sh_i2c_write, sh_i2c_set_bus_speed, CONFIG_SYS_I2C_SH_SPEED3, 0, 3) |
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#endif |
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#ifdef CONFIG_SYS_I2C_SH_BASE4 |
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U_BOOT_I2C_ADAP_COMPLETE(sh_4, sh_i2c_init, sh_i2c_probe, sh_i2c_read, |
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sh_i2c_write, sh_i2c_set_bus_speed, CONFIG_SYS_I2C_SH_SPEED4, 0, 4) |
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#endif
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