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653 lines
17 KiB
653 lines
17 KiB
// SPDX-License-Identifier: GPL-2.0 |
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/* |
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* Copyright 2006,2009 Freescale Semiconductor, Inc. |
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* |
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* 2012, Heiko Schocher, DENX Software Engineering, [email protected]. |
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* Changes for multibus/multiadapter I2C support. |
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*/ |
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|
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#include <common.h> |
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#include <command.h> |
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#include <i2c.h> /* Functional interface */ |
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#include <asm/io.h> |
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#include <asm/fsl_i2c.h> /* HW definitions */ |
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#include <clk.h> |
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#include <dm.h> |
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#include <mapmem.h> |
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|
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/* The maximum number of microseconds we will wait until another master has |
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* released the bus. If not defined in the board header file, then use a |
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* generic value. |
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*/ |
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#ifndef CONFIG_I2C_MBB_TIMEOUT |
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#define CONFIG_I2C_MBB_TIMEOUT 100000 |
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#endif |
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|
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/* The maximum number of microseconds we will wait for a read or write |
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* operation to complete. If not defined in the board header file, then use a |
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* generic value. |
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*/ |
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#ifndef CONFIG_I2C_TIMEOUT |
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#define CONFIG_I2C_TIMEOUT 100000 |
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#endif |
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#define I2C_READ_BIT 1 |
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#define I2C_WRITE_BIT 0 |
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|
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DECLARE_GLOBAL_DATA_PTR; |
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|
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#ifndef CONFIG_DM_I2C |
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static const struct fsl_i2c_base *i2c_base[4] = { |
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(struct fsl_i2c_base *)(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_I2C_OFFSET), |
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#ifdef CONFIG_SYS_FSL_I2C2_OFFSET |
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(struct fsl_i2c_base *)(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_I2C2_OFFSET), |
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#endif |
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#ifdef CONFIG_SYS_FSL_I2C3_OFFSET |
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(struct fsl_i2c_base *)(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_I2C3_OFFSET), |
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#endif |
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#ifdef CONFIG_SYS_FSL_I2C4_OFFSET |
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(struct fsl_i2c_base *)(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_I2C4_OFFSET) |
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#endif |
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}; |
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#endif |
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|
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/* I2C speed map for a DFSR value of 1 */ |
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|
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#ifdef __M68K__ |
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/* |
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* Map I2C frequency dividers to FDR and DFSR values |
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* |
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* This structure is used to define the elements of a table that maps I2C |
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* frequency divider (I2C clock rate divided by I2C bus speed) to a value to be |
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* programmed into the Frequency Divider Ratio (FDR) and Digital Filter |
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* Sampling Rate (DFSR) registers. |
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* |
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* The actual table should be defined in the board file, and it must be called |
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* fsl_i2c_speed_map[]. |
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* |
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* The last entry of the table must have a value of {-1, X}, where X is same |
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* FDR/DFSR values as the second-to-last entry. This guarantees that any |
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* search through the array will always find a match. |
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* |
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* The values of the divider must be in increasing numerical order, i.e. |
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* fsl_i2c_speed_map[x+1].divider > fsl_i2c_speed_map[x].divider. |
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* |
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* For this table, the values are based on a value of 1 for the DFSR |
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* register. See the application note AN2919 "Determining the I2C Frequency |
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* Divider Ratio for SCL" |
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* |
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* ColdFire I2C frequency dividers for FDR values are different from |
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* PowerPC. The protocol to use the I2C module is still the same. |
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* A different table is defined and are based on MCF5xxx user manual. |
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* |
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*/ |
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static const struct { |
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unsigned short divider; |
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u8 fdr; |
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} fsl_i2c_speed_map[] = { |
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{20, 32}, {22, 33}, {24, 34}, {26, 35}, |
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{28, 0}, {28, 36}, {30, 1}, {32, 37}, |
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{34, 2}, {36, 38}, {40, 3}, {40, 39}, |
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{44, 4}, {48, 5}, {48, 40}, {56, 6}, |
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{56, 41}, {64, 42}, {68, 7}, {72, 43}, |
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{80, 8}, {80, 44}, {88, 9}, {96, 41}, |
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{104, 10}, {112, 42}, {128, 11}, {128, 43}, |
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{144, 12}, {160, 13}, {160, 48}, {192, 14}, |
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{192, 49}, {224, 50}, {240, 15}, {256, 51}, |
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{288, 16}, {320, 17}, {320, 52}, {384, 18}, |
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{384, 53}, {448, 54}, {480, 19}, {512, 55}, |
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{576, 20}, {640, 21}, {640, 56}, {768, 22}, |
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{768, 57}, {960, 23}, {896, 58}, {1024, 59}, |
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{1152, 24}, {1280, 25}, {1280, 60}, {1536, 26}, |
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{1536, 61}, {1792, 62}, {1920, 27}, {2048, 63}, |
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{2304, 28}, {2560, 29}, {3072, 30}, {3840, 31}, |
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{-1, 31} |
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}; |
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#endif |
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|
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/** |
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* Set the I2C bus speed for a given I2C device |
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* |
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* @param base: the I2C device registers |
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* @i2c_clk: I2C bus clock frequency |
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* @speed: the desired speed of the bus |
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* |
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* The I2C device must be stopped before calling this function. |
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* |
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* The return value is the actual bus speed that is set. |
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*/ |
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static uint set_i2c_bus_speed(const struct fsl_i2c_base *base, |
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uint i2c_clk, uint speed) |
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{ |
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ushort divider = min(i2c_clk / speed, (uint)USHRT_MAX); |
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/* |
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* We want to choose an FDR/DFSR that generates an I2C bus speed that |
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* is equal to or lower than the requested speed. That means that we |
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* want the first divider that is equal to or greater than the |
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* calculated divider. |
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*/ |
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#ifdef __PPC__ |
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u8 dfsr, fdr = 0x31; /* Default if no FDR found */ |
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/* a, b and dfsr matches identifiers A,B and C respectively in AN2919 */ |
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ushort a, b, ga, gb; |
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ulong c_div, est_div; |
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|
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#ifdef CONFIG_FSL_I2C_CUSTOM_DFSR |
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dfsr = CONFIG_FSL_I2C_CUSTOM_DFSR; |
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#else |
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/* Condition 1: dfsr <= 50/T */ |
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dfsr = (5 * (i2c_clk / 1000)) / 100000; |
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#endif |
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#ifdef CONFIG_FSL_I2C_CUSTOM_FDR |
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fdr = CONFIG_FSL_I2C_CUSTOM_FDR; |
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speed = i2c_clk / divider; /* Fake something */ |
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#else |
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debug("Requested speed:%d, i2c_clk:%d\n", speed, i2c_clk); |
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if (!dfsr) |
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dfsr = 1; |
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est_div = ~0; |
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for (ga = 0x4, a = 10; a <= 30; ga++, a += 2) { |
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for (gb = 0; gb < 8; gb++) { |
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b = 16 << gb; |
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c_div = b * (a + ((3 * dfsr) / b) * 2); |
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if (c_div > divider && c_div < est_div) { |
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ushort bin_gb, bin_ga; |
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est_div = c_div; |
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bin_gb = gb << 2; |
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bin_ga = (ga & 0x3) | ((ga & 0x4) << 3); |
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fdr = bin_gb | bin_ga; |
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speed = i2c_clk / est_div; |
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debug("FDR: 0x%.2x, ", fdr); |
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debug("div: %ld, ", est_div); |
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debug("ga: 0x%x, gb: 0x%x, ", ga, gb); |
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debug("a: %d, b: %d, speed: %d\n", a, b, speed); |
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|
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/* Condition 2 not accounted for */ |
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debug("Tr <= %d ns\n", |
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(b - 3 * dfsr) * 1000000 / |
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(i2c_clk / 1000)); |
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} |
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} |
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if (a == 20) |
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a += 2; |
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if (a == 24) |
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a += 4; |
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} |
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debug("divider: %d, est_div: %ld, DFSR: %d\n", divider, est_div, dfsr); |
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debug("FDR: 0x%.2x, speed: %d\n", fdr, speed); |
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#endif |
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writeb(dfsr, &base->dfsrr); /* set default filter */ |
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writeb(fdr, &base->fdr); /* set bus speed */ |
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#else |
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uint i; |
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for (i = 0; i < ARRAY_SIZE(fsl_i2c_speed_map); i++) |
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if (fsl_i2c_speed_map[i].divider >= divider) { |
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u8 fdr; |
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fdr = fsl_i2c_speed_map[i].fdr; |
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speed = i2c_clk / fsl_i2c_speed_map[i].divider; |
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writeb(fdr, &base->fdr); /* set bus speed */ |
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break; |
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} |
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#endif |
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return speed; |
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} |
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#ifndef CONFIG_DM_I2C |
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static uint get_i2c_clock(int bus) |
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{ |
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if (bus) |
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return gd->arch.i2c2_clk; /* I2C2 clock */ |
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else |
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return gd->arch.i2c1_clk; /* I2C1 clock */ |
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} |
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#endif |
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static int fsl_i2c_fixup(const struct fsl_i2c_base *base) |
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{ |
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const unsigned long long timeout = usec2ticks(CONFIG_I2C_MBB_TIMEOUT); |
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unsigned long long timeval = 0; |
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int ret = -1; |
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uint flags = 0; |
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#ifdef CONFIG_SYS_FSL_ERRATUM_I2C_A004447 |
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uint svr = get_svr(); |
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if ((SVR_SOC_VER(svr) == SVR_8548 && IS_SVR_REV(svr, 3, 1)) || |
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(SVR_REV(svr) <= CONFIG_SYS_FSL_A004447_SVR_REV)) |
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flags = I2C_CR_BIT6; |
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#endif |
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writeb(I2C_CR_MEN | I2C_CR_MSTA, &base->cr); |
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timeval = get_ticks(); |
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while (!(readb(&base->sr) & I2C_SR_MBB)) { |
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if ((get_ticks() - timeval) > timeout) |
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goto err; |
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} |
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if (readb(&base->sr) & I2C_SR_MAL) { |
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/* SDA is stuck low */ |
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writeb(0, &base->cr); |
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udelay(100); |
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writeb(I2C_CR_MSTA | flags, &base->cr); |
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writeb(I2C_CR_MEN | I2C_CR_MSTA | flags, &base->cr); |
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} |
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readb(&base->dr); |
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timeval = get_ticks(); |
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while (!(readb(&base->sr) & I2C_SR_MIF)) { |
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if ((get_ticks() - timeval) > timeout) |
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goto err; |
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} |
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ret = 0; |
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err: |
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writeb(I2C_CR_MEN | flags, &base->cr); |
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writeb(0, &base->sr); |
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udelay(100); |
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return ret; |
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} |
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static void __i2c_init(const struct fsl_i2c_base *base, int speed, int |
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slaveadd, int i2c_clk, int busnum) |
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{ |
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const unsigned long long timeout = usec2ticks(CONFIG_I2C_MBB_TIMEOUT); |
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unsigned long long timeval; |
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#ifdef CONFIG_SYS_I2C_INIT_BOARD |
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/* Call board specific i2c bus reset routine before accessing the |
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* environment, which might be in a chip on that bus. For details |
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* about this problem see doc/I2C_Edge_Conditions. |
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*/ |
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i2c_init_board(); |
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#endif |
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writeb(0, &base->cr); /* stop I2C controller */ |
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udelay(5); /* let it shutdown in peace */ |
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set_i2c_bus_speed(base, i2c_clk, speed); |
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writeb(slaveadd << 1, &base->adr);/* write slave address */ |
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writeb(0x0, &base->sr); /* clear status register */ |
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writeb(I2C_CR_MEN, &base->cr); /* start I2C controller */ |
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timeval = get_ticks(); |
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while (readb(&base->sr) & I2C_SR_MBB) { |
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if ((get_ticks() - timeval) < timeout) |
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continue; |
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if (fsl_i2c_fixup(base)) |
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debug("i2c_init: BUS#%d failed to init\n", |
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busnum); |
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break; |
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} |
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} |
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static int i2c_wait4bus(const struct fsl_i2c_base *base) |
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{ |
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unsigned long long timeval = get_ticks(); |
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const unsigned long long timeout = usec2ticks(CONFIG_I2C_MBB_TIMEOUT); |
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while (readb(&base->sr) & I2C_SR_MBB) { |
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if ((get_ticks() - timeval) > timeout) |
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return -1; |
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} |
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return 0; |
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} |
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static int i2c_wait(const struct fsl_i2c_base *base, int write) |
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{ |
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u32 csr; |
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unsigned long long timeval = get_ticks(); |
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const unsigned long long timeout = usec2ticks(CONFIG_I2C_TIMEOUT); |
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do { |
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csr = readb(&base->sr); |
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if (!(csr & I2C_SR_MIF)) |
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continue; |
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/* Read again to allow register to stabilise */ |
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csr = readb(&base->sr); |
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writeb(0x0, &base->sr); |
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if (csr & I2C_SR_MAL) { |
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debug("%s: MAL\n", __func__); |
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return -1; |
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} |
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if (!(csr & I2C_SR_MCF)) { |
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debug("%s: unfinished\n", __func__); |
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return -1; |
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} |
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if (write == I2C_WRITE_BIT && (csr & I2C_SR_RXAK)) { |
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debug("%s: No RXACK\n", __func__); |
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return -1; |
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} |
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return 0; |
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} while ((get_ticks() - timeval) < timeout); |
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debug("%s: timed out\n", __func__); |
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return -1; |
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} |
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static int i2c_write_addr(const struct fsl_i2c_base *base, u8 dev, |
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u8 dir, int rsta) |
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{ |
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writeb(I2C_CR_MEN | I2C_CR_MSTA | I2C_CR_MTX |
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| (rsta ? I2C_CR_RSTA : 0), |
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&base->cr); |
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writeb((dev << 1) | dir, &base->dr); |
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if (i2c_wait(base, I2C_WRITE_BIT) < 0) |
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return 0; |
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return 1; |
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} |
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static int __i2c_write_data(const struct fsl_i2c_base *base, u8 *data, |
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int length) |
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{ |
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int i; |
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for (i = 0; i < length; i++) { |
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writeb(data[i], &base->dr); |
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if (i2c_wait(base, I2C_WRITE_BIT) < 0) |
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break; |
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} |
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return i; |
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} |
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static int __i2c_read_data(const struct fsl_i2c_base *base, u8 *data, |
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int length) |
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{ |
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int i; |
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writeb(I2C_CR_MEN | I2C_CR_MSTA | ((length == 1) ? I2C_CR_TXAK : 0), |
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&base->cr); |
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/* dummy read */ |
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readb(&base->dr); |
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for (i = 0; i < length; i++) { |
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if (i2c_wait(base, I2C_READ_BIT) < 0) |
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break; |
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/* Generate ack on last next to last byte */ |
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if (i == length - 2) |
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writeb(I2C_CR_MEN | I2C_CR_MSTA | I2C_CR_TXAK, |
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&base->cr); |
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/* Do not generate stop on last byte */ |
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if (i == length - 1) |
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writeb(I2C_CR_MEN | I2C_CR_MSTA | I2C_CR_MTX, |
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&base->cr); |
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data[i] = readb(&base->dr); |
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} |
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return i; |
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} |
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static int __i2c_read(const struct fsl_i2c_base *base, u8 chip_addr, u8 *offset, |
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int olen, u8 *data, int dlen) |
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{ |
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int ret = -1; /* signal error */ |
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if (i2c_wait4bus(base) < 0) |
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return -1; |
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/* Some drivers use offset lengths in excess of 4 bytes. These drivers |
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* adhere to the following convention: |
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* - the offset length is passed as negative (that is, the absolute |
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* value of olen is the actual offset length) |
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* - the offset itself is passed in data, which is overwritten by the |
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* subsequent read operation |
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*/ |
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if (olen < 0) { |
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if (i2c_write_addr(base, chip_addr, I2C_WRITE_BIT, 0) != 0) |
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ret = __i2c_write_data(base, data, -olen); |
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|
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if (ret != -olen) |
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return -1; |
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if (dlen && i2c_write_addr(base, chip_addr, |
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I2C_READ_BIT, 1) != 0) |
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ret = __i2c_read_data(base, data, dlen); |
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} else { |
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if ((!dlen || olen > 0) && |
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i2c_write_addr(base, chip_addr, I2C_WRITE_BIT, 0) != 0 && |
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__i2c_write_data(base, offset, olen) == olen) |
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ret = 0; /* No error so far */ |
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if (dlen && i2c_write_addr(base, chip_addr, I2C_READ_BIT, |
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olen ? 1 : 0) != 0) |
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ret = __i2c_read_data(base, data, dlen); |
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} |
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writeb(I2C_CR_MEN, &base->cr); |
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if (i2c_wait4bus(base)) /* Wait until STOP */ |
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debug("i2c_read: wait4bus timed out\n"); |
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if (ret == dlen) |
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return 0; |
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return -1; |
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} |
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static int __i2c_write(const struct fsl_i2c_base *base, u8 chip_addr, |
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u8 *offset, int olen, u8 *data, int dlen) |
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{ |
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int ret = -1; /* signal error */ |
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if (i2c_wait4bus(base) < 0) |
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return -1; |
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if (i2c_write_addr(base, chip_addr, I2C_WRITE_BIT, 0) != 0 && |
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__i2c_write_data(base, offset, olen) == olen) { |
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ret = __i2c_write_data(base, data, dlen); |
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} |
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writeb(I2C_CR_MEN, &base->cr); |
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if (i2c_wait4bus(base)) /* Wait until STOP */ |
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debug("i2c_write: wait4bus timed out\n"); |
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|
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if (ret == dlen) |
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return 0; |
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|
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return -1; |
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} |
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static int __i2c_probe_chip(const struct fsl_i2c_base *base, uchar chip) |
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{ |
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/* For unknown reason the controller will ACK when |
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* probing for a slave with the same address, so skip |
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* it. |
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*/ |
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if (chip == (readb(&base->adr) >> 1)) |
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return -1; |
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return __i2c_read(base, chip, 0, 0, NULL, 0); |
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} |
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static uint __i2c_set_bus_speed(const struct fsl_i2c_base *base, |
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uint speed, int i2c_clk) |
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{ |
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writeb(0, &base->cr); /* stop controller */ |
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set_i2c_bus_speed(base, i2c_clk, speed); |
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writeb(I2C_CR_MEN, &base->cr); /* start controller */ |
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|
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return 0; |
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} |
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|
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#ifndef CONFIG_DM_I2C |
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static void fsl_i2c_init(struct i2c_adapter *adap, int speed, int slaveadd) |
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{ |
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__i2c_init(i2c_base[adap->hwadapnr], speed, slaveadd, |
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get_i2c_clock(adap->hwadapnr), adap->hwadapnr); |
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} |
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|
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static int fsl_i2c_probe_chip(struct i2c_adapter *adap, uchar chip) |
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{ |
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return __i2c_probe_chip(i2c_base[adap->hwadapnr], chip); |
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} |
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static int fsl_i2c_read(struct i2c_adapter *adap, u8 chip_addr, uint offset, |
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int olen, u8 *data, int dlen) |
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{ |
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u8 *o = (u8 *)&offset; |
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|
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return __i2c_read(i2c_base[adap->hwadapnr], chip_addr, &o[4 - olen], |
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olen, data, dlen); |
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} |
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|
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static int fsl_i2c_write(struct i2c_adapter *adap, u8 chip_addr, uint offset, |
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int olen, u8 *data, int dlen) |
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{ |
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u8 *o = (u8 *)&offset; |
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|
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return __i2c_write(i2c_base[adap->hwadapnr], chip_addr, &o[4 - olen], |
|
olen, data, dlen); |
|
} |
|
|
|
static uint fsl_i2c_set_bus_speed(struct i2c_adapter *adap, uint speed) |
|
{ |
|
return __i2c_set_bus_speed(i2c_base[adap->hwadapnr], speed, |
|
get_i2c_clock(adap->hwadapnr)); |
|
} |
|
|
|
/* |
|
* Register fsl i2c adapters |
|
*/ |
|
U_BOOT_I2C_ADAP_COMPLETE(fsl_0, fsl_i2c_init, fsl_i2c_probe_chip, fsl_i2c_read, |
|
fsl_i2c_write, fsl_i2c_set_bus_speed, |
|
CONFIG_SYS_FSL_I2C_SPEED, CONFIG_SYS_FSL_I2C_SLAVE, |
|
0) |
|
#ifdef CONFIG_SYS_FSL_I2C2_OFFSET |
|
U_BOOT_I2C_ADAP_COMPLETE(fsl_1, fsl_i2c_init, fsl_i2c_probe_chip, fsl_i2c_read, |
|
fsl_i2c_write, fsl_i2c_set_bus_speed, |
|
CONFIG_SYS_FSL_I2C2_SPEED, CONFIG_SYS_FSL_I2C2_SLAVE, |
|
1) |
|
#endif |
|
#ifdef CONFIG_SYS_FSL_I2C3_OFFSET |
|
U_BOOT_I2C_ADAP_COMPLETE(fsl_2, fsl_i2c_init, fsl_i2c_probe_chip, fsl_i2c_read, |
|
fsl_i2c_write, fsl_i2c_set_bus_speed, |
|
CONFIG_SYS_FSL_I2C3_SPEED, CONFIG_SYS_FSL_I2C3_SLAVE, |
|
2) |
|
#endif |
|
#ifdef CONFIG_SYS_FSL_I2C4_OFFSET |
|
U_BOOT_I2C_ADAP_COMPLETE(fsl_3, fsl_i2c_init, fsl_i2c_probe_chip, fsl_i2c_read, |
|
fsl_i2c_write, fsl_i2c_set_bus_speed, |
|
CONFIG_SYS_FSL_I2C4_SPEED, CONFIG_SYS_FSL_I2C4_SLAVE, |
|
3) |
|
#endif |
|
#else /* CONFIG_DM_I2C */ |
|
static int fsl_i2c_probe_chip(struct udevice *bus, u32 chip_addr, |
|
u32 chip_flags) |
|
{ |
|
struct fsl_i2c_dev *dev = dev_get_priv(bus); |
|
|
|
return __i2c_probe_chip(dev->base, chip_addr); |
|
} |
|
|
|
static int fsl_i2c_set_bus_speed(struct udevice *bus, uint speed) |
|
{ |
|
struct fsl_i2c_dev *dev = dev_get_priv(bus); |
|
|
|
return __i2c_set_bus_speed(dev->base, speed, dev->i2c_clk); |
|
} |
|
|
|
static int fsl_i2c_ofdata_to_platdata(struct udevice *bus) |
|
{ |
|
struct fsl_i2c_dev *dev = dev_get_priv(bus); |
|
struct clk clock; |
|
|
|
dev->base = map_sysmem(dev_read_addr(bus), sizeof(struct fsl_i2c_base)); |
|
|
|
if (!dev->base) |
|
return -ENOMEM; |
|
|
|
dev->index = dev_read_u32_default(bus, "cell-index", -1); |
|
dev->slaveadd = dev_read_u32_default(bus, "u-boot,i2c-slave-addr", |
|
0x7f); |
|
dev->speed = dev_read_u32_default(bus, "clock-frequency", 400000); |
|
|
|
if (!clk_get_by_index(bus, 0, &clock)) |
|
dev->i2c_clk = clk_get_rate(&clock); |
|
else |
|
dev->i2c_clk = dev->index ? gd->arch.i2c2_clk : |
|
gd->arch.i2c1_clk; |
|
|
|
return 0; |
|
} |
|
|
|
static int fsl_i2c_probe(struct udevice *bus) |
|
{ |
|
struct fsl_i2c_dev *dev = dev_get_priv(bus); |
|
|
|
__i2c_init(dev->base, dev->speed, dev->slaveadd, dev->i2c_clk, |
|
dev->index); |
|
return 0; |
|
} |
|
|
|
static int fsl_i2c_xfer(struct udevice *bus, struct i2c_msg *msg, int nmsgs) |
|
{ |
|
struct fsl_i2c_dev *dev = dev_get_priv(bus); |
|
struct i2c_msg *dmsg, *omsg, dummy; |
|
|
|
memset(&dummy, 0, sizeof(struct i2c_msg)); |
|
|
|
/* We expect either two messages (one with an offset and one with the |
|
* actual data) or one message (just data) |
|
*/ |
|
if (nmsgs > 2 || nmsgs == 0) { |
|
debug("%s: Only one or two messages are supported.", __func__); |
|
return -1; |
|
} |
|
|
|
omsg = nmsgs == 1 ? &dummy : msg; |
|
dmsg = nmsgs == 1 ? msg : msg + 1; |
|
|
|
if (dmsg->flags & I2C_M_RD) |
|
return __i2c_read(dev->base, dmsg->addr, omsg->buf, omsg->len, |
|
dmsg->buf, dmsg->len); |
|
else |
|
return __i2c_write(dev->base, dmsg->addr, omsg->buf, omsg->len, |
|
dmsg->buf, dmsg->len); |
|
} |
|
|
|
static const struct dm_i2c_ops fsl_i2c_ops = { |
|
.xfer = fsl_i2c_xfer, |
|
.probe_chip = fsl_i2c_probe_chip, |
|
.set_bus_speed = fsl_i2c_set_bus_speed, |
|
}; |
|
|
|
static const struct udevice_id fsl_i2c_ids[] = { |
|
{ .compatible = "fsl-i2c", }, |
|
{ /* sentinel */ } |
|
}; |
|
|
|
U_BOOT_DRIVER(i2c_fsl) = { |
|
.name = "i2c_fsl", |
|
.id = UCLASS_I2C, |
|
.of_match = fsl_i2c_ids, |
|
.probe = fsl_i2c_probe, |
|
.ofdata_to_platdata = fsl_i2c_ofdata_to_platdata, |
|
.priv_auto_alloc_size = sizeof(struct fsl_i2c_dev), |
|
.ops = &fsl_i2c_ops, |
|
}; |
|
|
|
#endif /* CONFIG_DM_I2C */
|
|
|