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77 lines
1.8 KiB
77 lines
1.8 KiB
#ifndef _AT91_I2C_H |
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#define _AT91_I2C_H |
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#define TWI_CR_START BIT(0) /* Send a Start Condition */ |
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#define TWI_CR_MSEN BIT(2) /* Master Transfer Enable */ |
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#define TWI_CR_STOP BIT(1) /* Send a Stop Condition */ |
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#define TWI_CR_SVDIS BIT(5) /* Slave Transfer Disable */ |
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#define TWI_CR_SWRST BIT(7) /* Software Reset */ |
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#define TWI_CR_ACMEN BIT(16) /* Alternative Command Mode Enable */ |
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#define TWI_CR_ACMDIS BIT(17) /* Alternative Command Mode Disable */ |
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#define TWI_CR_LOCKCLR BIT(26) /* Lock Clear */ |
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#define TWI_MMR_MREAD BIT(12) /* Master Read Direction */ |
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#define TWI_MMR_IADRSZ_1 BIT(8) /* Internal Device Address Size */ |
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#define TWI_SR_TXCOMP BIT(0) /* Transmission Complete */ |
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#define TWI_SR_RXRDY BIT(1) /* Receive Holding Register Ready */ |
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#define TWI_SR_TXRDY BIT(2) /* Transmit Holding Register Ready */ |
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#define TWI_SR_OVRE BIT(6) /* Overrun Error */ |
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#define TWI_SR_UNRE BIT(7) /* Underrun Error */ |
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#define TWI_SR_NACK BIT(8) /* Not Acknowledged */ |
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#define TWI_SR_LOCK BIT(23) /* TWI Lock due to Frame Errors */ |
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#define TWI_ACR_DATAL(len) ((len) & 0xff) |
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#define TWI_ACR_DIR_READ BIT(8) |
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#define TWI_CWGR_HOLD_MAX 0x1f |
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#define TWI_CWGR_HOLD(x) (((x) & TWI_CWGR_HOLD_MAX) << 24) |
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struct at91_i2c_regs { |
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u32 cr; |
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u32 mmr; |
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u32 smr; |
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u32 iadr; |
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u32 cwgr; |
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u32 rev_0[3]; |
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u32 sr; |
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u32 ier; |
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u32 idr; |
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u32 imr; |
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u32 rhr; |
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u32 thr; |
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u32 smbtr; |
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u32 rev_1; |
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u32 acr; |
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u32 filtr; |
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u32 rev_2; |
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u32 swmr; |
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u32 fmr; |
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u32 flr; |
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u32 rev_3; |
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u32 fsr; |
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u32 fier; |
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u32 fidr; |
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u32 fimr; |
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u32 rev_4[29]; |
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u32 wpmr; |
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u32 wpsr; |
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u32 rev_5[6]; |
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}; |
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struct at91_i2c_pdata { |
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unsigned clk_max_div; |
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unsigned clk_offset; |
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}; |
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struct at91_i2c_bus { |
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struct at91_i2c_regs *regs; |
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u32 status; |
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ulong bus_clk_rate; |
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u32 clock_frequency; |
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u32 speed; |
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u32 cwgr_val; |
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const struct at91_i2c_pdata *pdata; |
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}; |
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#endif
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