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323 lines
6.8 KiB
323 lines
6.8 KiB
// SPDX-License-Identifier: GPL-2.0+ |
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/* |
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* Atmel I2C driver. |
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* |
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* (C) Copyright 2016 Songjun Wu <[email protected]> |
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*/ |
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#include <asm/io.h> |
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#include <common.h> |
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#include <clk.h> |
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#include <dm.h> |
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#include <errno.h> |
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#include <fdtdec.h> |
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#include <i2c.h> |
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#include <linux/bitops.h> |
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#include <mach/clk.h> |
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#include "at91_i2c.h" |
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DECLARE_GLOBAL_DATA_PTR; |
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#define I2C_TIMEOUT_MS 100 |
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static int at91_wait_for_xfer(struct at91_i2c_bus *bus, u32 status) |
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{ |
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struct at91_i2c_regs *reg = bus->regs; |
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ulong start_time = get_timer(0); |
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u32 sr; |
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bus->status = 0; |
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do { |
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sr = readl(®->sr); |
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bus->status |= sr; |
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if (sr & TWI_SR_NACK) |
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return -EREMOTEIO; |
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else if (sr & status) |
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return 0; |
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} while (get_timer(start_time) < I2C_TIMEOUT_MS); |
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return -ETIMEDOUT; |
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} |
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static int at91_i2c_xfer_msg(struct at91_i2c_bus *bus, struct i2c_msg *msg) |
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{ |
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struct at91_i2c_regs *reg = bus->regs; |
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bool is_read = msg->flags & I2C_M_RD; |
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u32 i; |
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int ret = 0; |
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readl(®->sr); |
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if (is_read) { |
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writel(TWI_CR_START, ®->cr); |
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for (i = 0; !ret && i < (msg->len - 1); i++) { |
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ret = at91_wait_for_xfer(bus, TWI_SR_RXRDY); |
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msg->buf[i] = readl(®->rhr); |
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} |
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if (ret) |
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goto error; |
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writel(TWI_CR_STOP, ®->cr); |
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ret = at91_wait_for_xfer(bus, TWI_SR_RXRDY); |
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if (ret) |
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goto error; |
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msg->buf[i] = readl(®->rhr); |
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} else { |
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writel(msg->buf[0], ®->thr); |
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ret = at91_wait_for_xfer(bus, TWI_SR_TXRDY); |
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for (i = 1; !ret && (i < msg->len); i++) { |
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writel(msg->buf[i], ®->thr); |
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ret = at91_wait_for_xfer(bus, TWI_SR_TXRDY); |
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} |
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if (ret) |
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goto error; |
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writel(TWI_CR_STOP, ®->cr); |
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} |
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if (!ret) |
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ret = at91_wait_for_xfer(bus, TWI_SR_TXCOMP); |
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if (ret) |
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goto error; |
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if (bus->status & (TWI_SR_OVRE | TWI_SR_UNRE | TWI_SR_LOCK)) { |
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ret = -EIO; |
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goto error; |
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} |
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return 0; |
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error: |
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if (bus->status & TWI_SR_LOCK) |
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writel(TWI_CR_LOCKCLR, ®->cr); |
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return ret; |
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} |
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static int at91_i2c_xfer(struct udevice *dev, struct i2c_msg *msg, int nmsgs) |
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{ |
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struct at91_i2c_bus *bus = dev_get_priv(dev); |
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struct at91_i2c_regs *reg = bus->regs; |
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struct i2c_msg *m_start = msg; |
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bool is_read; |
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u32 int_addr_flag = 0; |
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int ret = 0; |
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if (nmsgs == 2) { |
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int internal_address = 0; |
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int i; |
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/* 1st msg is put into the internal address, start with 2nd */ |
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m_start = &msg[1]; |
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/* the max length of internal address is 3 bytes */ |
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if (msg->len > 3) |
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return -EFAULT; |
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for (i = 0; i < msg->len; ++i) { |
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const unsigned addr = msg->buf[msg->len - 1 - i]; |
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internal_address |= addr << (8 * i); |
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int_addr_flag += TWI_MMR_IADRSZ_1; |
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} |
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writel(internal_address, ®->iadr); |
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} |
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is_read = m_start->flags & I2C_M_RD; |
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writel((m_start->addr << 16) | int_addr_flag | |
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(is_read ? TWI_MMR_MREAD : 0), ®->mmr); |
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ret = at91_i2c_xfer_msg(bus, m_start); |
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return ret; |
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} |
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/* |
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* Calculate symmetric clock as stated in datasheet: |
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* twi_clk = F_MAIN / (2 * (cdiv * (1 << ckdiv) + offset)) |
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*/ |
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static void at91_calc_i2c_clock(struct udevice *dev, int i2c_clk) |
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{ |
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struct at91_i2c_bus *bus = dev_get_priv(dev); |
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const struct at91_i2c_pdata *pdata = bus->pdata; |
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int offset = pdata->clk_offset; |
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int max_ckdiv = pdata->clk_max_div; |
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int ckdiv, cdiv, div; |
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unsigned long src_rate; |
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src_rate = bus->bus_clk_rate; |
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div = max(0, (int)DIV_ROUND_UP(src_rate, 2 * i2c_clk) - offset); |
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ckdiv = fls(div >> 8); |
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cdiv = div >> ckdiv; |
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if (ckdiv > max_ckdiv) { |
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ckdiv = max_ckdiv; |
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cdiv = 255; |
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} |
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bus->speed = DIV_ROUND_UP(src_rate, |
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(cdiv * (1 << ckdiv) + offset) * 2); |
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bus->cwgr_val = (ckdiv << 16) | (cdiv << 8) | cdiv; |
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} |
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static int at91_i2c_enable_clk(struct udevice *dev) |
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{ |
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struct at91_i2c_bus *bus = dev_get_priv(dev); |
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struct clk clk; |
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ulong clk_rate; |
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int ret; |
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ret = clk_get_by_index(dev, 0, &clk); |
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if (ret) |
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return -EINVAL; |
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ret = clk_enable(&clk); |
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if (ret) |
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return ret; |
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clk_rate = clk_get_rate(&clk); |
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if (!clk_rate) |
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return -EINVAL; |
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bus->bus_clk_rate = clk_rate; |
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clk_free(&clk); |
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return 0; |
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} |
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static int at91_i2c_set_bus_speed(struct udevice *dev, unsigned int speed) |
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{ |
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struct at91_i2c_bus *bus = dev_get_priv(dev); |
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at91_calc_i2c_clock(dev, speed); |
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writel(bus->cwgr_val, &bus->regs->cwgr); |
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return 0; |
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} |
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int at91_i2c_get_bus_speed(struct udevice *dev) |
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{ |
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struct at91_i2c_bus *bus = dev_get_priv(dev); |
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return bus->speed; |
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} |
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static int at91_i2c_ofdata_to_platdata(struct udevice *dev) |
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{ |
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const void *blob = gd->fdt_blob; |
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struct at91_i2c_bus *bus = dev_get_priv(dev); |
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int node = dev_of_offset(dev); |
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bus->regs = (struct at91_i2c_regs *)devfdt_get_addr(dev); |
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bus->pdata = (struct at91_i2c_pdata *)dev_get_driver_data(dev); |
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bus->clock_frequency = fdtdec_get_int(blob, node, |
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"clock-frequency", 100000); |
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return 0; |
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} |
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static const struct dm_i2c_ops at91_i2c_ops = { |
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.xfer = at91_i2c_xfer, |
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.set_bus_speed = at91_i2c_set_bus_speed, |
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.get_bus_speed = at91_i2c_get_bus_speed, |
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}; |
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static int at91_i2c_probe(struct udevice *dev) |
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{ |
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struct at91_i2c_bus *bus = dev_get_priv(dev); |
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struct at91_i2c_regs *reg = bus->regs; |
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int ret; |
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ret = at91_i2c_enable_clk(dev); |
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if (ret) |
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return ret; |
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writel(TWI_CR_SWRST, ®->cr); |
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at91_calc_i2c_clock(dev, bus->clock_frequency); |
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writel(bus->cwgr_val, ®->cwgr); |
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writel(TWI_CR_MSEN, ®->cr); |
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writel(TWI_CR_SVDIS, ®->cr); |
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return 0; |
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} |
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static const struct at91_i2c_pdata at91rm9200_config = { |
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.clk_max_div = 5, |
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.clk_offset = 3, |
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}; |
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static const struct at91_i2c_pdata at91sam9261_config = { |
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.clk_max_div = 5, |
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.clk_offset = 4, |
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}; |
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static const struct at91_i2c_pdata at91sam9260_config = { |
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.clk_max_div = 7, |
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.clk_offset = 4, |
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}; |
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static const struct at91_i2c_pdata at91sam9g20_config = { |
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.clk_max_div = 7, |
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.clk_offset = 4, |
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}; |
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static const struct at91_i2c_pdata at91sam9g10_config = { |
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.clk_max_div = 7, |
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.clk_offset = 4, |
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}; |
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static const struct at91_i2c_pdata at91sam9x5_config = { |
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.clk_max_div = 7, |
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.clk_offset = 4, |
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}; |
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static const struct at91_i2c_pdata sama5d4_config = { |
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.clk_max_div = 7, |
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.clk_offset = 4, |
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}; |
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static const struct at91_i2c_pdata sama5d2_config = { |
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.clk_max_div = 7, |
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.clk_offset = 3, |
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}; |
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static const struct udevice_id at91_i2c_ids[] = { |
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{ .compatible = "atmel,at91rm9200-i2c", .data = (long)&at91rm9200_config }, |
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{ .compatible = "atmel,at91sam9260-i2c", .data = (long)&at91sam9260_config }, |
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{ .compatible = "atmel,at91sam9261-i2c", .data = (long)&at91sam9261_config }, |
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{ .compatible = "atmel,at91sam9g20-i2c", .data = (long)&at91sam9g20_config }, |
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{ .compatible = "atmel,at91sam9g10-i2c", .data = (long)&at91sam9g10_config }, |
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{ .compatible = "atmel,at91sam9x5-i2c", .data = (long)&at91sam9x5_config }, |
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{ .compatible = "atmel,sama5d4-i2c", .data = (long)&sama5d4_config }, |
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{ .compatible = "atmel,sama5d2-i2c", .data = (long)&sama5d2_config }, |
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{ } |
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}; |
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U_BOOT_DRIVER(i2c_at91) = { |
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.name = "i2c_at91", |
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.id = UCLASS_I2C, |
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.of_match = at91_i2c_ids, |
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.probe = at91_i2c_probe, |
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.ofdata_to_platdata = at91_i2c_ofdata_to_platdata, |
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.per_child_auto_alloc_size = sizeof(struct dm_i2c_chip), |
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.priv_auto_alloc_size = sizeof(struct at91_i2c_bus), |
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.ops = &at91_i2c_ops, |
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};
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