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77 lines
2.7 KiB
77 lines
2.7 KiB
/* |
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* Copyright (C) 2007 Google, Inc. |
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* Author: Brian Swetland <[email protected]> |
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* |
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* This software is licensed under the terms of the GNU General Public |
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* License version 2, as published by the Free Software Foundation, and |
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* may be copied, distributed, and modified under those terms. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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*/ |
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#ifndef __LINUX_USB_GADGET_MSM72K_UDC_H__ |
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#define __LINUX_USB_GADGET_MSM72K_UDC_H__ |
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/* USB phy selector - in TCSR address range */ |
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#define USB2_PHY_SEL 0xfd4ab000 |
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#define USB_AHBBURST (MSM_USB_BASE + 0x0090) |
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#define USB_AHBMODE (MSM_USB_BASE + 0x0098) |
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#define USB_GENCONFIG_2 (MSM_USB_BASE + 0x00a0) |
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#define ULPI_TX_PKT_EN_CLR_FIX BIT(19) |
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#define USB_CAPLENGTH (MSM_USB_BASE + 0x0100) /* 8 bit */ |
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#define USB_USBCMD (MSM_USB_BASE + 0x0140) |
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#define USB_PORTSC (MSM_USB_BASE + 0x0184) |
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#define USB_OTGSC (MSM_USB_BASE + 0x01A4) |
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#define USB_USBMODE (MSM_USB_BASE + 0x01A8) |
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#define USB_PHY_CTRL (MSM_USB_BASE + 0x0240) |
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#define USB_PHY_CTRL2 (MSM_USB_BASE + 0x0278) |
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#define GENCONFIG_2_SESS_VLD_CTRL_EN BIT(7) |
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#define USBCMD_SESS_VLD_CTRL BIT(25) |
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#define USBCMD_RESET 2 |
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#define USB_USBINTR (MSM_USB_BASE + 0x0148) |
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#define PORTSC_PHCD (1 << 23) /* phy suspend mode */ |
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#define PORTSC_PTS_MASK (3 << 30) |
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#define PORTSC_PTS_ULPI (2 << 30) |
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#define PORTSC_PTS_SERIAL (3 << 30) |
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#define USB_ULPI_VIEWPORT (MSM_USB_BASE + 0x0170) |
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#define ULPI_RUN (1 << 30) |
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#define ULPI_WRITE (1 << 29) |
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#define ULPI_READ (0 << 29) |
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#define ULPI_ADDR(n) (((n) & 255) << 16) |
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#define ULPI_DATA(n) ((n) & 255) |
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#define ULPI_DATA_READ(n) (((n) >> 8) & 255) |
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/* synopsys 28nm phy registers */ |
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#define ULPI_PWR_CLK_MNG_REG 0x88 |
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#define OTG_COMP_DISABLE BIT(0) |
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#define ULPI_MISC_A 0x96 |
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#define ULPI_MISC_A_VBUSVLDEXTSEL BIT(1) |
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#define ULPI_MISC_A_VBUSVLDEXT BIT(0) |
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#define ASYNC_INTR_CTRL (1 << 29) /* Enable async interrupt */ |
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#define ULPI_STP_CTRL (1 << 30) /* Block communication with PHY */ |
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#define PHY_RETEN (1 << 1) /* PHY retention enable/disable */ |
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#define PHY_POR_ASSERT (1 << 0) /* USB2 28nm PHY POR ASSERT */ |
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/* OTG definitions */ |
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#define OTGSC_INTSTS_MASK (0x7f << 16) |
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#define OTGSC_ID (1 << 8) |
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#define OTGSC_BSV (1 << 11) |
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#define OTGSC_IDIS (1 << 16) |
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#define OTGSC_BSVIS (1 << 19) |
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#define OTGSC_IDIE (1 << 24) |
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#define OTGSC_BSVIE (1 << 27) |
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#endif /* __LINUX_USB_GADGET_MSM72K_UDC_H__ */
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