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124 lines
4.0 KiB
124 lines
4.0 KiB
/* SPDX-License-Identifier: GPL-2.0 */ |
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/* |
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* Copyright (C) 2019 STMicroelectronics |
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* Author(s): Amelie Delaunay <[email protected]>. |
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*/ |
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#ifndef MFD_STMFX_H |
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#define MFD_STMFX_H |
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#include <linux/regmap.h> |
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/* General */ |
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#define STMFX_REG_CHIP_ID 0x00 /* R */ |
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#define STMFX_REG_FW_VERSION_MSB 0x01 /* R */ |
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#define STMFX_REG_FW_VERSION_LSB 0x02 /* R */ |
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#define STMFX_REG_SYS_CTRL 0x40 /* RW */ |
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/* IRQ output management */ |
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#define STMFX_REG_IRQ_OUT_PIN 0x41 /* RW */ |
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#define STMFX_REG_IRQ_SRC_EN 0x42 /* RW */ |
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#define STMFX_REG_IRQ_PENDING 0x08 /* R */ |
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#define STMFX_REG_IRQ_ACK 0x44 /* RW */ |
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/* GPIO management */ |
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#define STMFX_REG_IRQ_GPI_PENDING1 0x0C /* R */ |
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#define STMFX_REG_IRQ_GPI_PENDING2 0x0D /* R */ |
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#define STMFX_REG_IRQ_GPI_PENDING3 0x0E /* R */ |
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#define STMFX_REG_GPIO_STATE1 0x10 /* R */ |
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#define STMFX_REG_GPIO_STATE2 0x11 /* R */ |
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#define STMFX_REG_GPIO_STATE3 0x12 /* R */ |
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#define STMFX_REG_IRQ_GPI_SRC1 0x48 /* RW */ |
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#define STMFX_REG_IRQ_GPI_SRC2 0x49 /* RW */ |
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#define STMFX_REG_IRQ_GPI_SRC3 0x4A /* RW */ |
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#define STMFX_REG_IRQ_GPI_EVT1 0x4C /* RW */ |
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#define STMFX_REG_IRQ_GPI_EVT2 0x4D /* RW */ |
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#define STMFX_REG_IRQ_GPI_EVT3 0x4E /* RW */ |
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#define STMFX_REG_IRQ_GPI_TYPE1 0x50 /* RW */ |
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#define STMFX_REG_IRQ_GPI_TYPE2 0x51 /* RW */ |
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#define STMFX_REG_IRQ_GPI_TYPE3 0x52 /* RW */ |
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#define STMFX_REG_IRQ_GPI_ACK1 0x54 /* RW */ |
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#define STMFX_REG_IRQ_GPI_ACK2 0x55 /* RW */ |
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#define STMFX_REG_IRQ_GPI_ACK3 0x56 /* RW */ |
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#define STMFX_REG_GPIO_DIR1 0x60 /* RW */ |
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#define STMFX_REG_GPIO_DIR2 0x61 /* RW */ |
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#define STMFX_REG_GPIO_DIR3 0x62 /* RW */ |
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#define STMFX_REG_GPIO_TYPE1 0x64 /* RW */ |
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#define STMFX_REG_GPIO_TYPE2 0x65 /* RW */ |
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#define STMFX_REG_GPIO_TYPE3 0x66 /* RW */ |
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#define STMFX_REG_GPIO_PUPD1 0x68 /* RW */ |
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#define STMFX_REG_GPIO_PUPD2 0x69 /* RW */ |
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#define STMFX_REG_GPIO_PUPD3 0x6A /* RW */ |
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#define STMFX_REG_GPO_SET1 0x6C /* RW */ |
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#define STMFX_REG_GPO_SET2 0x6D /* RW */ |
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#define STMFX_REG_GPO_SET3 0x6E /* RW */ |
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#define STMFX_REG_GPO_CLR1 0x70 /* RW */ |
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#define STMFX_REG_GPO_CLR2 0x71 /* RW */ |
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#define STMFX_REG_GPO_CLR3 0x72 /* RW */ |
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#define STMFX_REG_MAX 0xB0 |
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/* MFX boot time is around 10ms, so after reset, we have to wait this delay */ |
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#define STMFX_BOOT_TIME_MS 10 |
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/* STMFX_REG_CHIP_ID bitfields */ |
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#define STMFX_REG_CHIP_ID_MASK GENMASK(7, 0) |
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/* STMFX_REG_SYS_CTRL bitfields */ |
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#define STMFX_REG_SYS_CTRL_GPIO_EN BIT(0) |
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#define STMFX_REG_SYS_CTRL_TS_EN BIT(1) |
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#define STMFX_REG_SYS_CTRL_IDD_EN BIT(2) |
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#define STMFX_REG_SYS_CTRL_ALTGPIO_EN BIT(3) |
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#define STMFX_REG_SYS_CTRL_SWRST BIT(7) |
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/* STMFX_REG_IRQ_OUT_PIN bitfields */ |
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#define STMFX_REG_IRQ_OUT_PIN_TYPE BIT(0) /* 0-OD 1-PP */ |
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#define STMFX_REG_IRQ_OUT_PIN_POL BIT(1) /* 0-active LOW 1-active HIGH */ |
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/* STMFX_REG_IRQ_(SRC_EN/PENDING/ACK) bit shift */ |
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enum stmfx_irqs { |
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STMFX_REG_IRQ_SRC_EN_GPIO = 0, |
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STMFX_REG_IRQ_SRC_EN_IDD, |
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STMFX_REG_IRQ_SRC_EN_ERROR, |
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STMFX_REG_IRQ_SRC_EN_TS_DET, |
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STMFX_REG_IRQ_SRC_EN_TS_NE, |
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STMFX_REG_IRQ_SRC_EN_TS_TH, |
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STMFX_REG_IRQ_SRC_EN_TS_FULL, |
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STMFX_REG_IRQ_SRC_EN_TS_OVF, |
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STMFX_REG_IRQ_SRC_MAX, |
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}; |
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enum stmfx_functions { |
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STMFX_FUNC_GPIO = BIT(0), /* GPIO[15:0] */ |
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STMFX_FUNC_ALTGPIO_LOW = BIT(1), /* aGPIO[3:0] */ |
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STMFX_FUNC_ALTGPIO_HIGH = BIT(2), /* aGPIO[7:4] */ |
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STMFX_FUNC_TS = BIT(3), |
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STMFX_FUNC_IDD = BIT(4), |
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}; |
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/** |
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* struct stmfx_ddata - STMFX MFD structure |
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* @device: device reference used for logs |
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* @map: register map |
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* @vdd: STMFX power supply |
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* @irq_domain: IRQ domain |
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* @lock: IRQ bus lock |
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* @irq_src: cache of IRQ_SRC_EN register for bus_lock |
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* @bkp_sysctrl: backup of SYS_CTRL register for suspend/resume |
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* @bkp_irqoutpin: backup of IRQ_OUT_PIN register for suspend/resume |
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*/ |
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struct stmfx { |
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struct device *dev; |
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struct regmap *map; |
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struct regulator *vdd; |
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int irq; |
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struct irq_domain *irq_domain; |
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struct mutex lock; /* IRQ bus lock */ |
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u8 irq_src; |
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#ifdef CONFIG_PM |
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u8 bkp_sysctrl; |
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u8 bkp_irqoutpin; |
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#endif |
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}; |
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int stmfx_function_enable(struct stmfx *stmfx, u32 func); |
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int stmfx_function_disable(struct stmfx *stmfx, u32 func); |
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#endif
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