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143 lines
5.8 KiB
143 lines
5.8 KiB
/* SPDX-License-Identifier: GPL-2.0 */ |
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/* |
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* Copyright (C) STMicroelectronics 2016 |
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* Author: Benjamin Gaignard <[email protected]> |
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*/ |
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#ifndef _LINUX_STM32_GPTIMER_H_ |
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#define _LINUX_STM32_GPTIMER_H_ |
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#include <linux/clk.h> |
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#include <linux/dmaengine.h> |
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#include <linux/dma-mapping.h> |
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#include <linux/regmap.h> |
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#define TIM_CR1 0x00 /* Control Register 1 */ |
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#define TIM_CR2 0x04 /* Control Register 2 */ |
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#define TIM_SMCR 0x08 /* Slave mode control reg */ |
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#define TIM_DIER 0x0C /* DMA/interrupt register */ |
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#define TIM_SR 0x10 /* Status register */ |
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#define TIM_EGR 0x14 /* Event Generation Reg */ |
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#define TIM_CCMR1 0x18 /* Capt/Comp 1 Mode Reg */ |
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#define TIM_CCMR2 0x1C /* Capt/Comp 2 Mode Reg */ |
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#define TIM_CCER 0x20 /* Capt/Comp Enable Reg */ |
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#define TIM_CNT 0x24 /* Counter */ |
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#define TIM_PSC 0x28 /* Prescaler */ |
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#define TIM_ARR 0x2c /* Auto-Reload Register */ |
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#define TIM_CCR1 0x34 /* Capt/Comp Register 1 */ |
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#define TIM_CCR2 0x38 /* Capt/Comp Register 2 */ |
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#define TIM_CCR3 0x3C /* Capt/Comp Register 3 */ |
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#define TIM_CCR4 0x40 /* Capt/Comp Register 4 */ |
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#define TIM_BDTR 0x44 /* Break and Dead-Time Reg */ |
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#define TIM_DCR 0x48 /* DMA control register */ |
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#define TIM_DMAR 0x4C /* DMA register for transfer */ |
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#define TIM_CR1_CEN BIT(0) /* Counter Enable */ |
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#define TIM_CR1_DIR BIT(4) /* Counter Direction */ |
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#define TIM_CR1_ARPE BIT(7) /* Auto-reload Preload Ena */ |
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#define TIM_CR2_MMS (BIT(4) | BIT(5) | BIT(6)) /* Master mode selection */ |
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#define TIM_CR2_MMS2 GENMASK(23, 20) /* Master mode selection 2 */ |
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#define TIM_SMCR_SMS (BIT(0) | BIT(1) | BIT(2)) /* Slave mode selection */ |
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#define TIM_SMCR_TS (BIT(4) | BIT(5) | BIT(6)) /* Trigger selection */ |
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#define TIM_DIER_UIE BIT(0) /* Update interrupt */ |
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#define TIM_DIER_UDE BIT(8) /* Update DMA request Enable */ |
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#define TIM_DIER_CC1DE BIT(9) /* CC1 DMA request Enable */ |
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#define TIM_DIER_CC2DE BIT(10) /* CC2 DMA request Enable */ |
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#define TIM_DIER_CC3DE BIT(11) /* CC3 DMA request Enable */ |
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#define TIM_DIER_CC4DE BIT(12) /* CC4 DMA request Enable */ |
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#define TIM_DIER_COMDE BIT(13) /* COM DMA request Enable */ |
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#define TIM_DIER_TDE BIT(14) /* Trigger DMA request Enable */ |
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#define TIM_SR_UIF BIT(0) /* Update interrupt flag */ |
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#define TIM_EGR_UG BIT(0) /* Update Generation */ |
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#define TIM_CCMR_PE BIT(3) /* Channel Preload Enable */ |
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#define TIM_CCMR_M1 (BIT(6) | BIT(5)) /* Channel PWM Mode 1 */ |
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#define TIM_CCMR_CC1S (BIT(0) | BIT(1)) /* Capture/compare 1 sel */ |
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#define TIM_CCMR_IC1PSC GENMASK(3, 2) /* Input capture 1 prescaler */ |
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#define TIM_CCMR_CC2S (BIT(8) | BIT(9)) /* Capture/compare 2 sel */ |
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#define TIM_CCMR_IC2PSC GENMASK(11, 10) /* Input capture 2 prescaler */ |
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#define TIM_CCMR_CC1S_TI1 BIT(0) /* IC1/IC3 selects TI1/TI3 */ |
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#define TIM_CCMR_CC1S_TI2 BIT(1) /* IC1/IC3 selects TI2/TI4 */ |
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#define TIM_CCMR_CC2S_TI2 BIT(8) /* IC2/IC4 selects TI2/TI4 */ |
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#define TIM_CCMR_CC2S_TI1 BIT(9) /* IC2/IC4 selects TI1/TI3 */ |
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#define TIM_CCER_CC1E BIT(0) /* Capt/Comp 1 out Ena */ |
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#define TIM_CCER_CC1P BIT(1) /* Capt/Comp 1 Polarity */ |
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#define TIM_CCER_CC1NE BIT(2) /* Capt/Comp 1N out Ena */ |
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#define TIM_CCER_CC1NP BIT(3) /* Capt/Comp 1N Polarity */ |
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#define TIM_CCER_CC2E BIT(4) /* Capt/Comp 2 out Ena */ |
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#define TIM_CCER_CC2P BIT(5) /* Capt/Comp 2 Polarity */ |
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#define TIM_CCER_CC3E BIT(8) /* Capt/Comp 3 out Ena */ |
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#define TIM_CCER_CC3P BIT(9) /* Capt/Comp 3 Polarity */ |
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#define TIM_CCER_CC4E BIT(12) /* Capt/Comp 4 out Ena */ |
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#define TIM_CCER_CC4P BIT(13) /* Capt/Comp 4 Polarity */ |
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#define TIM_CCER_CCXE (BIT(0) | BIT(4) | BIT(8) | BIT(12)) |
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#define TIM_BDTR_BKE(x) BIT(12 + (x) * 12) /* Break input enable */ |
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#define TIM_BDTR_BKP(x) BIT(13 + (x) * 12) /* Break input polarity */ |
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#define TIM_BDTR_AOE BIT(14) /* Automatic Output Enable */ |
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#define TIM_BDTR_MOE BIT(15) /* Main Output Enable */ |
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#define TIM_BDTR_BKF(x) (0xf << (16 + (x) * 4)) |
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#define TIM_DCR_DBA GENMASK(4, 0) /* DMA base addr */ |
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#define TIM_DCR_DBL GENMASK(12, 8) /* DMA burst len */ |
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#define MAX_TIM_PSC 0xFFFF |
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#define MAX_TIM_ICPSC 0x3 |
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#define TIM_CR2_MMS_SHIFT 4 |
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#define TIM_CR2_MMS2_SHIFT 20 |
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#define TIM_SMCR_SMS_SLAVE_MODE_DISABLED 0 /* counts on internal clock when CEN=1 */ |
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#define TIM_SMCR_SMS_ENCODER_MODE_1 1 /* counts TI1FP1 edges, depending on TI2FP2 level */ |
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#define TIM_SMCR_SMS_ENCODER_MODE_2 2 /* counts TI2FP2 edges, depending on TI1FP1 level */ |
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#define TIM_SMCR_SMS_ENCODER_MODE_3 3 /* counts on both TI1FP1 and TI2FP2 edges */ |
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#define TIM_SMCR_TS_SHIFT 4 |
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#define TIM_BDTR_BKF_MASK 0xF |
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#define TIM_BDTR_BKF_SHIFT(x) (16 + (x) * 4) |
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enum stm32_timers_dmas { |
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STM32_TIMERS_DMA_CH1, |
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STM32_TIMERS_DMA_CH2, |
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STM32_TIMERS_DMA_CH3, |
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STM32_TIMERS_DMA_CH4, |
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STM32_TIMERS_DMA_UP, |
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STM32_TIMERS_DMA_TRIG, |
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STM32_TIMERS_DMA_COM, |
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STM32_TIMERS_MAX_DMAS, |
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}; |
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/** |
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* struct stm32_timers_dma - STM32 timer DMA handling. |
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* @completion: end of DMA transfer completion |
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* @phys_base: control registers physical base address |
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* @lock: protect DMA access |
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* @chan: DMA channel in use |
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* @chans: DMA channels available for this timer instance |
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*/ |
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struct stm32_timers_dma { |
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struct completion completion; |
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phys_addr_t phys_base; |
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struct mutex lock; |
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struct dma_chan *chan; |
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struct dma_chan *chans[STM32_TIMERS_MAX_DMAS]; |
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}; |
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struct stm32_timers { |
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struct clk *clk; |
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struct regmap *regmap; |
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u32 max_arr; |
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struct stm32_timers_dma dma; /* Only to be used by the parent */ |
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}; |
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#if IS_REACHABLE(CONFIG_MFD_STM32_TIMERS) |
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int stm32_timers_dma_burst_read(struct device *dev, u32 *buf, |
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enum stm32_timers_dmas id, u32 reg, |
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unsigned int num_reg, unsigned int bursts, |
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unsigned long tmo_ms); |
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#else |
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static inline int stm32_timers_dma_burst_read(struct device *dev, u32 *buf, |
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enum stm32_timers_dmas id, |
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u32 reg, |
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unsigned int num_reg, |
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unsigned int bursts, |
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unsigned long tmo_ms) |
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{ |
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return -ENODEV; |
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} |
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#endif |
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#endif
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