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140 lines
4.3 KiB
140 lines
4.3 KiB
/* SPDX-License-Identifier: GPL-2.0-or-later */ |
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/* Copyright (C) 2021 ROHM Semiconductors */ |
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#ifndef __LINUX_MFD_BD957X_H__ |
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#define __LINUX_MFD_BD957X_H__ |
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enum { |
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BD957X_VD50, |
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BD957X_VD18, |
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BD957X_VDDDR, |
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BD957X_VD10, |
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BD957X_VOUTL1, |
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BD957X_VOUTS1, |
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}; |
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/* |
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* The BD9576 has own IRQ 'blocks' for: |
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* - I2C/thermal, |
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* - Over voltage protection |
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* - Short-circuit protection |
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* - Over current protection |
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* - Over voltage detection |
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* - Under voltage detection |
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* - Under voltage protection |
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* - 'system interrupt'. |
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* |
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* Each of the blocks have a status register giving more accurate IRQ source |
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* information - for example which of the regulators have over-voltage. |
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* |
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* On top of this, there is "main IRQ" status register where each bit indicates |
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* which of sub-blocks have active IRQs. Fine. That would fit regmap-irq main |
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* status handling. Except that: |
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* - Only some sub-IRQs can be masked. |
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* - The IRQ informs us about fault-condition, not when fault state changes. |
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* The IRQ line it is kept asserted until the detected condition is acked |
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* AND cleared in HW. This is annoying for IRQs like the one informing high |
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* temperature because if IRQ is not disabled it keeps the CPU in IRQ |
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* handling loop. |
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* |
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* For now we do just use the main-IRQ register as source for our IRQ |
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* information and bind the regmap-irq to this. We leave fine-grained sub-IRQ |
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* register handling to handlers in sub-devices. The regulator driver shall |
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* read which regulators are source for problem - or if the detected error is |
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* regulator temperature error. The sub-drivers do also handle masking of "sub- |
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* IRQs" if this is supported/needed. |
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* |
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* To overcome the problem with HW keeping IRQ asserted we do call |
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* disable_irq_nosync() from sub-device handler and add a delayed work to |
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* re-enable IRQ roughly 1 second later. This should keep our CPU out of |
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* busy-loop. |
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*/ |
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#define IRQS_SILENT_MS 1000 |
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enum { |
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BD9576_INT_THERM, |
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BD9576_INT_OVP, |
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BD9576_INT_SCP, |
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BD9576_INT_OCP, |
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BD9576_INT_OVD, |
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BD9576_INT_UVD, |
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BD9576_INT_UVP, |
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BD9576_INT_SYS, |
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}; |
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#define BD957X_REG_SMRB_ASSERT 0x15 |
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#define BD957X_REG_PMIC_INTERNAL_STAT 0x20 |
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#define BD957X_REG_INT_THERM_STAT 0x23 |
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#define BD957X_REG_INT_THERM_MASK 0x24 |
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#define BD957X_REG_INT_OVP_STAT 0x25 |
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#define BD957X_REG_INT_SCP_STAT 0x26 |
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#define BD957X_REG_INT_OCP_STAT 0x27 |
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#define BD957X_REG_INT_OVD_STAT 0x28 |
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#define BD957X_REG_INT_UVD_STAT 0x29 |
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#define BD957X_REG_INT_UVP_STAT 0x2a |
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#define BD957X_REG_INT_SYS_STAT 0x2b |
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#define BD957X_REG_INT_SYS_MASK 0x2c |
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#define BD957X_REG_INT_MAIN_STAT 0x30 |
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#define BD957X_REG_INT_MAIN_MASK 0x31 |
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#define UVD_IRQ_VALID_MASK 0x6F |
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#define OVD_IRQ_VALID_MASK 0x2F |
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#define BD957X_MASK_INT_MAIN_THERM BIT(0) |
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#define BD957X_MASK_INT_MAIN_OVP BIT(1) |
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#define BD957X_MASK_INT_MAIN_SCP BIT(2) |
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#define BD957X_MASK_INT_MAIN_OCP BIT(3) |
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#define BD957X_MASK_INT_MAIN_OVD BIT(4) |
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#define BD957X_MASK_INT_MAIN_UVD BIT(5) |
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#define BD957X_MASK_INT_MAIN_UVP BIT(6) |
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#define BD957X_MASK_INT_MAIN_SYS BIT(7) |
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#define BD957X_MASK_INT_ALL 0xff |
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#define BD957X_REG_WDT_CONF 0x16 |
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#define BD957X_REG_POW_TRIGGER1 0x41 |
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#define BD957X_REG_POW_TRIGGER2 0x42 |
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#define BD957X_REG_POW_TRIGGER3 0x43 |
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#define BD957X_REG_POW_TRIGGER4 0x44 |
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#define BD957X_REG_POW_TRIGGERL1 0x45 |
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#define BD957X_REG_POW_TRIGGERS1 0x46 |
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#define BD957X_REGULATOR_EN_MASK 0xff |
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#define BD957X_REGULATOR_DIS_VAL 0xff |
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#define BD957X_VSEL_REG_MASK 0xff |
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#define BD957X_MASK_VOUT1_TUNE 0x87 |
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#define BD957X_MASK_VOUT2_TUNE 0x87 |
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#define BD957X_MASK_VOUT3_TUNE 0x1f |
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#define BD957X_MASK_VOUT4_TUNE 0x1f |
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#define BD957X_MASK_VOUTL1_TUNE 0x87 |
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#define BD957X_REG_VOUT1_TUNE 0x50 |
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#define BD957X_REG_VOUT2_TUNE 0x53 |
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#define BD957X_REG_VOUT3_TUNE 0x56 |
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#define BD957X_REG_VOUT4_TUNE 0x59 |
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#define BD957X_REG_VOUTL1_TUNE 0x5c |
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#define BD9576_REG_VOUT1_OVD 0x51 |
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#define BD9576_REG_VOUT1_UVD 0x52 |
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#define BD9576_REG_VOUT2_OVD 0x54 |
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#define BD9576_REG_VOUT2_UVD 0x55 |
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#define BD9576_REG_VOUT3_OVD 0x57 |
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#define BD9576_REG_VOUT3_UVD 0x58 |
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#define BD9576_REG_VOUT4_OVD 0x5a |
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#define BD9576_REG_VOUT4_UVD 0x5b |
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#define BD9576_REG_VOUTL1_OVD 0x5d |
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#define BD9576_REG_VOUTL1_UVD 0x5e |
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#define BD9576_MASK_XVD 0x7f |
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#define BD9576_REG_VOUT1S_OCW 0x5f |
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#define BD9576_REG_VOUT1S_OCP 0x60 |
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#define BD9576_MASK_VOUT1S_OCW 0x3f |
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#define BD9576_MASK_VOUT1S_OCP 0x3f |
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#define BD957X_MAX_REGISTER 0x61 |
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#endif
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