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162 lines
4.8 KiB
162 lines
4.8 KiB
/* SPDX-License-Identifier: GPL-2.0 */ |
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/* |
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* Intel MAX 10 Board Management Controller chip. |
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* |
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* Copyright (C) 2018-2020 Intel Corporation, Inc. |
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*/ |
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#ifndef __MFD_INTEL_M10_BMC_H |
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#define __MFD_INTEL_M10_BMC_H |
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#include <linux/regmap.h> |
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#define M10BMC_LEGACY_BUILD_VER 0x300468 |
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#define M10BMC_SYS_BASE 0x300800 |
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#define M10BMC_SYS_END 0x300fff |
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#define M10BMC_FLASH_BASE 0x10000000 |
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#define M10BMC_FLASH_END 0x1fffffff |
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#define M10BMC_MEM_END M10BMC_FLASH_END |
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#define M10BMC_STAGING_BASE 0x18000000 |
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#define M10BMC_STAGING_SIZE 0x3800000 |
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/* Register offset of system registers */ |
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#define NIOS2_FW_VERSION 0x0 |
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#define M10BMC_MAC_LOW 0x10 |
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#define M10BMC_MAC_BYTE4 GENMASK(7, 0) |
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#define M10BMC_MAC_BYTE3 GENMASK(15, 8) |
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#define M10BMC_MAC_BYTE2 GENMASK(23, 16) |
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#define M10BMC_MAC_BYTE1 GENMASK(31, 24) |
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#define M10BMC_MAC_HIGH 0x14 |
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#define M10BMC_MAC_BYTE6 GENMASK(7, 0) |
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#define M10BMC_MAC_BYTE5 GENMASK(15, 8) |
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#define M10BMC_MAC_COUNT GENMASK(23, 16) |
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#define M10BMC_TEST_REG 0x3c |
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#define M10BMC_BUILD_VER 0x68 |
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#define M10BMC_VER_MAJOR_MSK GENMASK(23, 16) |
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#define M10BMC_VER_PCB_INFO_MSK GENMASK(31, 24) |
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#define M10BMC_VER_LEGACY_INVALID 0xffffffff |
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/* Secure update doorbell register, in system register region */ |
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#define M10BMC_DOORBELL 0x400 |
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/* Authorization Result register, in system register region */ |
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#define M10BMC_AUTH_RESULT 0x404 |
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/* Doorbell register fields */ |
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#define DRBL_RSU_REQUEST BIT(0) |
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#define DRBL_RSU_PROGRESS GENMASK(7, 4) |
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#define DRBL_HOST_STATUS GENMASK(11, 8) |
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#define DRBL_RSU_STATUS GENMASK(23, 16) |
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#define DRBL_PKVL_EEPROM_LOAD_SEC BIT(24) |
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#define DRBL_PKVL1_POLL_EN BIT(25) |
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#define DRBL_PKVL2_POLL_EN BIT(26) |
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#define DRBL_CONFIG_SEL BIT(28) |
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#define DRBL_REBOOT_REQ BIT(29) |
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#define DRBL_REBOOT_DISABLED BIT(30) |
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/* Progress states */ |
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#define RSU_PROG_IDLE 0x0 |
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#define RSU_PROG_PREPARE 0x1 |
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#define RSU_PROG_READY 0x3 |
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#define RSU_PROG_AUTHENTICATING 0x4 |
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#define RSU_PROG_COPYING 0x5 |
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#define RSU_PROG_UPDATE_CANCEL 0x6 |
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#define RSU_PROG_PROGRAM_KEY_HASH 0x7 |
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#define RSU_PROG_RSU_DONE 0x8 |
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#define RSU_PROG_PKVL_PROM_DONE 0x9 |
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/* Device and error states */ |
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#define RSU_STAT_NORMAL 0x0 |
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#define RSU_STAT_TIMEOUT 0x1 |
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#define RSU_STAT_AUTH_FAIL 0x2 |
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#define RSU_STAT_COPY_FAIL 0x3 |
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#define RSU_STAT_FATAL 0x4 |
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#define RSU_STAT_PKVL_REJECT 0x5 |
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#define RSU_STAT_NON_INC 0x6 |
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#define RSU_STAT_ERASE_FAIL 0x7 |
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#define RSU_STAT_WEAROUT 0x8 |
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#define RSU_STAT_NIOS_OK 0x80 |
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#define RSU_STAT_USER_OK 0x81 |
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#define RSU_STAT_FACTORY_OK 0x82 |
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#define RSU_STAT_USER_FAIL 0x83 |
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#define RSU_STAT_FACTORY_FAIL 0x84 |
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#define RSU_STAT_NIOS_FLASH_ERR 0x85 |
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#define RSU_STAT_FPGA_FLASH_ERR 0x86 |
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#define HOST_STATUS_IDLE 0x0 |
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#define HOST_STATUS_WRITE_DONE 0x1 |
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#define HOST_STATUS_ABORT_RSU 0x2 |
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#define rsu_prog(doorbell) FIELD_GET(DRBL_RSU_PROGRESS, doorbell) |
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#define rsu_stat(doorbell) FIELD_GET(DRBL_RSU_STATUS, doorbell) |
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/* interval 100ms and timeout 5s */ |
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#define NIOS_HANDSHAKE_INTERVAL_US (100 * 1000) |
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#define NIOS_HANDSHAKE_TIMEOUT_US (5 * 1000 * 1000) |
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/* RSU PREP Timeout (2 minutes) to erase flash staging area */ |
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#define RSU_PREP_INTERVAL_MS 100 |
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#define RSU_PREP_TIMEOUT_MS (2 * 60 * 1000) |
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/* RSU Complete Timeout (40 minutes) for full flash update */ |
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#define RSU_COMPLETE_INTERVAL_MS 1000 |
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#define RSU_COMPLETE_TIMEOUT_MS (40 * 60 * 1000) |
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/* Addresses for security related data in FLASH */ |
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#define BMC_REH_ADDR 0x17ffc004 |
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#define BMC_PROG_ADDR 0x17ffc000 |
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#define BMC_PROG_MAGIC 0x5746 |
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#define SR_REH_ADDR 0x17ffd004 |
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#define SR_PROG_ADDR 0x17ffd000 |
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#define SR_PROG_MAGIC 0x5253 |
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#define PR_REH_ADDR 0x17ffe004 |
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#define PR_PROG_ADDR 0x17ffe000 |
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#define PR_PROG_MAGIC 0x5250 |
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/* Address of 4KB inverted bit vector containing staging area FLASH count */ |
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#define STAGING_FLASH_COUNT 0x17ffb000 |
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/** |
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* struct intel_m10bmc - Intel MAX 10 BMC parent driver data structure |
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* @dev: this device |
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* @regmap: the regmap used to access registers by m10bmc itself |
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*/ |
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struct intel_m10bmc { |
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struct device *dev; |
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struct regmap *regmap; |
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}; |
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/* |
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* register access helper functions. |
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* |
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* m10bmc_raw_read - read m10bmc register per addr |
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* m10bmc_sys_read - read m10bmc system register per offset |
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*/ |
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static inline int |
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m10bmc_raw_read(struct intel_m10bmc *m10bmc, unsigned int addr, |
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unsigned int *val) |
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{ |
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int ret; |
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ret = regmap_read(m10bmc->regmap, addr, val); |
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if (ret) |
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dev_err(m10bmc->dev, "fail to read raw reg %x: %d\n", |
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addr, ret); |
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return ret; |
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} |
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/* |
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* The base of the system registers could be configured by HW developers, and |
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* in HW SPEC, the base is not added to the addresses of the system registers. |
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* |
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* This macro helps to simplify the accessing of the system registers. And if |
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* the base is reconfigured in HW, SW developers could simply change the |
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* M10BMC_SYS_BASE accordingly. |
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*/ |
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#define m10bmc_sys_read(m10bmc, offset, val) \ |
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m10bmc_raw_read(m10bmc, M10BMC_SYS_BASE + (offset), val) |
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#endif /* __MFD_INTEL_M10_BMC_H */
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