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852 lines
21 KiB
852 lines
21 KiB
// SPDX-License-Identifier: GPL-2.0 |
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#include <linux/kernel.h> |
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#include <linux/module.h> |
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#include <linux/io.h> |
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#include <linux/platform_device.h> |
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#include <linux/console.h> |
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#include <linux/sysrq.h> |
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#include <linux/serial_core.h> |
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#include <linux/tty_flip.h> |
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#include <linux/slab.h> |
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#include <linux/clk.h> |
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#include <linux/of.h> |
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#include <linux/of_device.h> |
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|
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#include <linux/platform_data/efm32-uart.h> |
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|
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#define DRIVER_NAME "efm32-uart" |
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#define DEV_NAME "ttyefm" |
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#define UARTn_CTRL 0x00 |
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#define UARTn_CTRL_SYNC 0x0001 |
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#define UARTn_CTRL_TXBIL 0x1000 |
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#define UARTn_FRAME 0x04 |
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#define UARTn_FRAME_DATABITS__MASK 0x000f |
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#define UARTn_FRAME_DATABITS(n) ((n) - 3) |
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#define UARTn_FRAME_PARITY__MASK 0x0300 |
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#define UARTn_FRAME_PARITY_NONE 0x0000 |
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#define UARTn_FRAME_PARITY_EVEN 0x0200 |
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#define UARTn_FRAME_PARITY_ODD 0x0300 |
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#define UARTn_FRAME_STOPBITS_HALF 0x0000 |
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#define UARTn_FRAME_STOPBITS_ONE 0x1000 |
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#define UARTn_FRAME_STOPBITS_TWO 0x3000 |
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|
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#define UARTn_CMD 0x0c |
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#define UARTn_CMD_RXEN 0x0001 |
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#define UARTn_CMD_RXDIS 0x0002 |
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#define UARTn_CMD_TXEN 0x0004 |
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#define UARTn_CMD_TXDIS 0x0008 |
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#define UARTn_STATUS 0x10 |
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#define UARTn_STATUS_TXENS 0x0002 |
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#define UARTn_STATUS_TXC 0x0020 |
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#define UARTn_STATUS_TXBL 0x0040 |
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#define UARTn_STATUS_RXDATAV 0x0080 |
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#define UARTn_CLKDIV 0x14 |
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#define UARTn_RXDATAX 0x18 |
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#define UARTn_RXDATAX_RXDATA__MASK 0x01ff |
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#define UARTn_RXDATAX_PERR 0x4000 |
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#define UARTn_RXDATAX_FERR 0x8000 |
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/* |
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* This is a software only flag used for ignore_status_mask and |
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* read_status_mask! It's used for breaks that the hardware doesn't report |
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* explicitly. |
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*/ |
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#define SW_UARTn_RXDATAX_BERR 0x2000 |
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#define UARTn_TXDATA 0x34 |
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#define UARTn_IF 0x40 |
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#define UARTn_IF_TXC 0x0001 |
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#define UARTn_IF_TXBL 0x0002 |
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#define UARTn_IF_RXDATAV 0x0004 |
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#define UARTn_IF_RXOF 0x0010 |
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#define UARTn_IFS 0x44 |
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#define UARTn_IFC 0x48 |
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#define UARTn_IEN 0x4c |
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#define UARTn_ROUTE 0x54 |
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#define UARTn_ROUTE_LOCATION__MASK 0x0700 |
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#define UARTn_ROUTE_LOCATION(n) (((n) << 8) & UARTn_ROUTE_LOCATION__MASK) |
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#define UARTn_ROUTE_RXPEN 0x0001 |
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#define UARTn_ROUTE_TXPEN 0x0002 |
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struct efm32_uart_port { |
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struct uart_port port; |
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unsigned int txirq; |
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struct clk *clk; |
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struct efm32_uart_pdata pdata; |
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}; |
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#define to_efm_port(_port) container_of(_port, struct efm32_uart_port, port) |
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#define efm_debug(efm_port, format, arg...) \ |
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dev_dbg(efm_port->port.dev, format, ##arg) |
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|
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static void efm32_uart_write32(struct efm32_uart_port *efm_port, |
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u32 value, unsigned offset) |
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{ |
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writel_relaxed(value, efm_port->port.membase + offset); |
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} |
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static u32 efm32_uart_read32(struct efm32_uart_port *efm_port, |
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unsigned offset) |
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{ |
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return readl_relaxed(efm_port->port.membase + offset); |
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} |
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static unsigned int efm32_uart_tx_empty(struct uart_port *port) |
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{ |
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struct efm32_uart_port *efm_port = to_efm_port(port); |
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u32 status = efm32_uart_read32(efm_port, UARTn_STATUS); |
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if (status & UARTn_STATUS_TXC) |
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return TIOCSER_TEMT; |
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else |
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return 0; |
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} |
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static void efm32_uart_set_mctrl(struct uart_port *port, unsigned int mctrl) |
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{ |
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/* sorry, neither handshaking lines nor loop functionallity */ |
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} |
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static unsigned int efm32_uart_get_mctrl(struct uart_port *port) |
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{ |
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/* sorry, no handshaking lines available */ |
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return TIOCM_CAR | TIOCM_CTS | TIOCM_DSR; |
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} |
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static void efm32_uart_stop_tx(struct uart_port *port) |
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{ |
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struct efm32_uart_port *efm_port = to_efm_port(port); |
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u32 ien = efm32_uart_read32(efm_port, UARTn_IEN); |
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efm32_uart_write32(efm_port, UARTn_CMD_TXDIS, UARTn_CMD); |
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ien &= ~(UARTn_IF_TXC | UARTn_IF_TXBL); |
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efm32_uart_write32(efm_port, ien, UARTn_IEN); |
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} |
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static void efm32_uart_tx_chars(struct efm32_uart_port *efm_port) |
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{ |
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struct uart_port *port = &efm_port->port; |
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struct circ_buf *xmit = &port->state->xmit; |
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while (efm32_uart_read32(efm_port, UARTn_STATUS) & |
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UARTn_STATUS_TXBL) { |
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if (port->x_char) { |
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port->icount.tx++; |
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efm32_uart_write32(efm_port, port->x_char, |
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UARTn_TXDATA); |
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port->x_char = 0; |
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continue; |
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} |
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if (!uart_circ_empty(xmit) && !uart_tx_stopped(port)) { |
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port->icount.tx++; |
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efm32_uart_write32(efm_port, xmit->buf[xmit->tail], |
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UARTn_TXDATA); |
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xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); |
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} else |
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break; |
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} |
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if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) |
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uart_write_wakeup(port); |
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if (!port->x_char && uart_circ_empty(xmit) && |
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efm32_uart_read32(efm_port, UARTn_STATUS) & |
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UARTn_STATUS_TXC) |
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efm32_uart_stop_tx(port); |
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} |
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static void efm32_uart_start_tx(struct uart_port *port) |
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{ |
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struct efm32_uart_port *efm_port = to_efm_port(port); |
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u32 ien; |
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efm32_uart_write32(efm_port, |
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UARTn_IF_TXBL | UARTn_IF_TXC, UARTn_IFC); |
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ien = efm32_uart_read32(efm_port, UARTn_IEN); |
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efm32_uart_write32(efm_port, |
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ien | UARTn_IF_TXBL | UARTn_IF_TXC, UARTn_IEN); |
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efm32_uart_write32(efm_port, UARTn_CMD_TXEN, UARTn_CMD); |
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efm32_uart_tx_chars(efm_port); |
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} |
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static void efm32_uart_stop_rx(struct uart_port *port) |
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{ |
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struct efm32_uart_port *efm_port = to_efm_port(port); |
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efm32_uart_write32(efm_port, UARTn_CMD_RXDIS, UARTn_CMD); |
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} |
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static void efm32_uart_break_ctl(struct uart_port *port, int ctl) |
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{ |
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/* not possible without fiddling with gpios */ |
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} |
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static void efm32_uart_rx_chars(struct efm32_uart_port *efm_port) |
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{ |
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struct uart_port *port = &efm_port->port; |
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while (efm32_uart_read32(efm_port, UARTn_STATUS) & |
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UARTn_STATUS_RXDATAV) { |
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u32 rxdata = efm32_uart_read32(efm_port, UARTn_RXDATAX); |
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int flag = 0; |
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/* |
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* This is a reserved bit and I only saw it read as 0. But to be |
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* sure not to be confused too much by new devices adhere to the |
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* warning in the reference manual that reserved bits might |
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* read as 1 in the future. |
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*/ |
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rxdata &= ~SW_UARTn_RXDATAX_BERR; |
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port->icount.rx++; |
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if ((rxdata & UARTn_RXDATAX_FERR) && |
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!(rxdata & UARTn_RXDATAX_RXDATA__MASK)) { |
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rxdata |= SW_UARTn_RXDATAX_BERR; |
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port->icount.brk++; |
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if (uart_handle_break(port)) |
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continue; |
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} else if (rxdata & UARTn_RXDATAX_PERR) |
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port->icount.parity++; |
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else if (rxdata & UARTn_RXDATAX_FERR) |
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port->icount.frame++; |
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rxdata &= port->read_status_mask; |
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if (rxdata & SW_UARTn_RXDATAX_BERR) |
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flag = TTY_BREAK; |
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else if (rxdata & UARTn_RXDATAX_PERR) |
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flag = TTY_PARITY; |
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else if (rxdata & UARTn_RXDATAX_FERR) |
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flag = TTY_FRAME; |
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else if (uart_handle_sysrq_char(port, |
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rxdata & UARTn_RXDATAX_RXDATA__MASK)) |
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continue; |
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if ((rxdata & port->ignore_status_mask) == 0) |
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tty_insert_flip_char(&port->state->port, |
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rxdata & UARTn_RXDATAX_RXDATA__MASK, flag); |
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} |
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} |
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static irqreturn_t efm32_uart_rxirq(int irq, void *data) |
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{ |
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struct efm32_uart_port *efm_port = data; |
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u32 irqflag = efm32_uart_read32(efm_port, UARTn_IF); |
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int handled = IRQ_NONE; |
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struct uart_port *port = &efm_port->port; |
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struct tty_port *tport = &port->state->port; |
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spin_lock(&port->lock); |
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if (irqflag & UARTn_IF_RXDATAV) { |
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efm32_uart_write32(efm_port, UARTn_IF_RXDATAV, UARTn_IFC); |
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efm32_uart_rx_chars(efm_port); |
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handled = IRQ_HANDLED; |
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} |
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if (irqflag & UARTn_IF_RXOF) { |
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efm32_uart_write32(efm_port, UARTn_IF_RXOF, UARTn_IFC); |
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port->icount.overrun++; |
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tty_insert_flip_char(tport, 0, TTY_OVERRUN); |
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handled = IRQ_HANDLED; |
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} |
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spin_unlock(&port->lock); |
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tty_flip_buffer_push(tport); |
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return handled; |
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} |
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static irqreturn_t efm32_uart_txirq(int irq, void *data) |
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{ |
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struct efm32_uart_port *efm_port = data; |
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u32 irqflag = efm32_uart_read32(efm_port, UARTn_IF); |
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/* TXBL doesn't need to be cleared */ |
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if (irqflag & UARTn_IF_TXC) |
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efm32_uart_write32(efm_port, UARTn_IF_TXC, UARTn_IFC); |
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if (irqflag & (UARTn_IF_TXC | UARTn_IF_TXBL)) { |
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efm32_uart_tx_chars(efm_port); |
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return IRQ_HANDLED; |
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} else |
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return IRQ_NONE; |
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} |
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static int efm32_uart_startup(struct uart_port *port) |
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{ |
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struct efm32_uart_port *efm_port = to_efm_port(port); |
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int ret; |
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ret = clk_enable(efm_port->clk); |
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if (ret) { |
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efm_debug(efm_port, "failed to enable clk\n"); |
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goto err_clk_enable; |
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} |
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port->uartclk = clk_get_rate(efm_port->clk); |
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/* Enable pins at configured location */ |
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efm32_uart_write32(efm_port, |
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UARTn_ROUTE_LOCATION(efm_port->pdata.location) | |
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UARTn_ROUTE_RXPEN | UARTn_ROUTE_TXPEN, |
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UARTn_ROUTE); |
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ret = request_irq(port->irq, efm32_uart_rxirq, 0, |
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DRIVER_NAME, efm_port); |
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if (ret) { |
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efm_debug(efm_port, "failed to register rxirq\n"); |
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goto err_request_irq_rx; |
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} |
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/* disable all irqs */ |
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efm32_uart_write32(efm_port, 0, UARTn_IEN); |
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ret = request_irq(efm_port->txirq, efm32_uart_txirq, 0, |
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DRIVER_NAME, efm_port); |
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if (ret) { |
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efm_debug(efm_port, "failed to register txirq\n"); |
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free_irq(port->irq, efm_port); |
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err_request_irq_rx: |
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clk_disable(efm_port->clk); |
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} else { |
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efm32_uart_write32(efm_port, |
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UARTn_IF_RXDATAV | UARTn_IF_RXOF, UARTn_IEN); |
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efm32_uart_write32(efm_port, UARTn_CMD_RXEN, UARTn_CMD); |
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} |
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err_clk_enable: |
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return ret; |
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} |
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static void efm32_uart_shutdown(struct uart_port *port) |
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{ |
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struct efm32_uart_port *efm_port = to_efm_port(port); |
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efm32_uart_write32(efm_port, 0, UARTn_IEN); |
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free_irq(port->irq, efm_port); |
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clk_disable(efm_port->clk); |
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} |
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static void efm32_uart_set_termios(struct uart_port *port, |
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struct ktermios *new, struct ktermios *old) |
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{ |
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struct efm32_uart_port *efm_port = to_efm_port(port); |
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unsigned long flags; |
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unsigned baud; |
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u32 clkdiv; |
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u32 frame = 0; |
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/* no modem control lines */ |
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new->c_cflag &= ~(CRTSCTS | CMSPAR); |
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baud = uart_get_baud_rate(port, new, old, |
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DIV_ROUND_CLOSEST(port->uartclk, 16 * 8192), |
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DIV_ROUND_CLOSEST(port->uartclk, 16)); |
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switch (new->c_cflag & CSIZE) { |
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case CS5: |
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frame |= UARTn_FRAME_DATABITS(5); |
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break; |
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case CS6: |
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frame |= UARTn_FRAME_DATABITS(6); |
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break; |
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case CS7: |
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frame |= UARTn_FRAME_DATABITS(7); |
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break; |
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case CS8: |
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frame |= UARTn_FRAME_DATABITS(8); |
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break; |
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} |
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if (new->c_cflag & CSTOPB) |
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/* the receiver only verifies the first stop bit */ |
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frame |= UARTn_FRAME_STOPBITS_TWO; |
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else |
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frame |= UARTn_FRAME_STOPBITS_ONE; |
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if (new->c_cflag & PARENB) { |
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if (new->c_cflag & PARODD) |
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frame |= UARTn_FRAME_PARITY_ODD; |
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else |
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frame |= UARTn_FRAME_PARITY_EVEN; |
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} else |
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frame |= UARTn_FRAME_PARITY_NONE; |
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/* |
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* the 6 lowest bits of CLKDIV are dc, bit 6 has value 0.25. |
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* port->uartclk <= 14e6, so 4 * port->uartclk doesn't overflow. |
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*/ |
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clkdiv = (DIV_ROUND_CLOSEST(4 * port->uartclk, 16 * baud) - 4) << 6; |
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spin_lock_irqsave(&port->lock, flags); |
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efm32_uart_write32(efm_port, |
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UARTn_CMD_TXDIS | UARTn_CMD_RXDIS, UARTn_CMD); |
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port->read_status_mask = UARTn_RXDATAX_RXDATA__MASK; |
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if (new->c_iflag & INPCK) |
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port->read_status_mask |= |
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UARTn_RXDATAX_FERR | UARTn_RXDATAX_PERR; |
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if (new->c_iflag & (IGNBRK | BRKINT | PARMRK)) |
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port->read_status_mask |= SW_UARTn_RXDATAX_BERR; |
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port->ignore_status_mask = 0; |
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if (new->c_iflag & IGNPAR) |
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port->ignore_status_mask |= |
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UARTn_RXDATAX_FERR | UARTn_RXDATAX_PERR; |
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if (new->c_iflag & IGNBRK) |
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port->ignore_status_mask |= SW_UARTn_RXDATAX_BERR; |
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uart_update_timeout(port, new->c_cflag, baud); |
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efm32_uart_write32(efm_port, UARTn_CTRL_TXBIL, UARTn_CTRL); |
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efm32_uart_write32(efm_port, frame, UARTn_FRAME); |
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efm32_uart_write32(efm_port, clkdiv, UARTn_CLKDIV); |
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efm32_uart_write32(efm_port, UARTn_CMD_TXEN | UARTn_CMD_RXEN, |
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UARTn_CMD); |
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spin_unlock_irqrestore(&port->lock, flags); |
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} |
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static const char *efm32_uart_type(struct uart_port *port) |
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{ |
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return port->type == PORT_EFMUART ? "efm32-uart" : NULL; |
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} |
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static void efm32_uart_release_port(struct uart_port *port) |
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{ |
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struct efm32_uart_port *efm_port = to_efm_port(port); |
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clk_unprepare(efm_port->clk); |
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clk_put(efm_port->clk); |
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iounmap(port->membase); |
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} |
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static int efm32_uart_request_port(struct uart_port *port) |
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{ |
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struct efm32_uart_port *efm_port = to_efm_port(port); |
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int ret; |
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port->membase = ioremap(port->mapbase, 60); |
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if (!efm_port->port.membase) { |
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ret = -ENOMEM; |
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efm_debug(efm_port, "failed to remap\n"); |
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goto err_ioremap; |
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} |
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efm_port->clk = clk_get(port->dev, NULL); |
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if (IS_ERR(efm_port->clk)) { |
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ret = PTR_ERR(efm_port->clk); |
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efm_debug(efm_port, "failed to get clock\n"); |
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goto err_clk_get; |
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} |
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ret = clk_prepare(efm_port->clk); |
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if (ret) { |
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clk_put(efm_port->clk); |
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err_clk_get: |
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|
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iounmap(port->membase); |
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err_ioremap: |
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return ret; |
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} |
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return 0; |
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} |
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static void efm32_uart_config_port(struct uart_port *port, int type) |
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{ |
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if (type & UART_CONFIG_TYPE && |
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!efm32_uart_request_port(port)) |
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port->type = PORT_EFMUART; |
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} |
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static int efm32_uart_verify_port(struct uart_port *port, |
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struct serial_struct *serinfo) |
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{ |
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int ret = 0; |
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|
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if (serinfo->type != PORT_UNKNOWN && serinfo->type != PORT_EFMUART) |
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ret = -EINVAL; |
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return ret; |
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} |
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static const struct uart_ops efm32_uart_pops = { |
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.tx_empty = efm32_uart_tx_empty, |
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.set_mctrl = efm32_uart_set_mctrl, |
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.get_mctrl = efm32_uart_get_mctrl, |
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.stop_tx = efm32_uart_stop_tx, |
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.start_tx = efm32_uart_start_tx, |
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.stop_rx = efm32_uart_stop_rx, |
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.break_ctl = efm32_uart_break_ctl, |
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.startup = efm32_uart_startup, |
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.shutdown = efm32_uart_shutdown, |
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.set_termios = efm32_uart_set_termios, |
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.type = efm32_uart_type, |
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.release_port = efm32_uart_release_port, |
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.request_port = efm32_uart_request_port, |
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.config_port = efm32_uart_config_port, |
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.verify_port = efm32_uart_verify_port, |
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}; |
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|
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static struct efm32_uart_port *efm32_uart_ports[5]; |
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|
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#ifdef CONFIG_SERIAL_EFM32_UART_CONSOLE |
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static void efm32_uart_console_putchar(struct uart_port *port, int ch) |
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{ |
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struct efm32_uart_port *efm_port = to_efm_port(port); |
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unsigned int timeout = 0x400; |
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u32 status; |
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|
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while (1) { |
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status = efm32_uart_read32(efm_port, UARTn_STATUS); |
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|
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if (status & UARTn_STATUS_TXBL) |
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break; |
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if (!timeout--) |
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return; |
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} |
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efm32_uart_write32(efm_port, ch, UARTn_TXDATA); |
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} |
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static void efm32_uart_console_write(struct console *co, const char *s, |
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unsigned int count) |
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{ |
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struct efm32_uart_port *efm_port = efm32_uart_ports[co->index]; |
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u32 status = efm32_uart_read32(efm_port, UARTn_STATUS); |
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unsigned int timeout = 0x400; |
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|
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if (!(status & UARTn_STATUS_TXENS)) |
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efm32_uart_write32(efm_port, UARTn_CMD_TXEN, UARTn_CMD); |
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|
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uart_console_write(&efm_port->port, s, count, |
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efm32_uart_console_putchar); |
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/* Wait for the transmitter to become empty */ |
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while (1) { |
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u32 status = efm32_uart_read32(efm_port, UARTn_STATUS); |
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if (status & UARTn_STATUS_TXC) |
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break; |
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if (!timeout--) |
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break; |
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} |
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if (!(status & UARTn_STATUS_TXENS)) |
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efm32_uart_write32(efm_port, UARTn_CMD_TXDIS, UARTn_CMD); |
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} |
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static void efm32_uart_console_get_options(struct efm32_uart_port *efm_port, |
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int *baud, int *parity, int *bits) |
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{ |
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u32 ctrl = efm32_uart_read32(efm_port, UARTn_CTRL); |
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u32 route, clkdiv, frame; |
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|
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if (ctrl & UARTn_CTRL_SYNC) |
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/* not operating in async mode */ |
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return; |
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route = efm32_uart_read32(efm_port, UARTn_ROUTE); |
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if (!(route & UARTn_ROUTE_TXPEN)) |
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/* tx pin not routed */ |
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return; |
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clkdiv = efm32_uart_read32(efm_port, UARTn_CLKDIV); |
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*baud = DIV_ROUND_CLOSEST(4 * efm_port->port.uartclk, |
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16 * (4 + (clkdiv >> 6))); |
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frame = efm32_uart_read32(efm_port, UARTn_FRAME); |
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switch (frame & UARTn_FRAME_PARITY__MASK) { |
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case UARTn_FRAME_PARITY_ODD: |
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*parity = 'o'; |
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break; |
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case UARTn_FRAME_PARITY_EVEN: |
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*parity = 'e'; |
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break; |
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default: |
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*parity = 'n'; |
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} |
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*bits = (frame & UARTn_FRAME_DATABITS__MASK) - |
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UARTn_FRAME_DATABITS(4) + 4; |
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efm_debug(efm_port, "get_opts: options=%d%c%d\n", |
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*baud, *parity, *bits); |
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} |
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static int efm32_uart_console_setup(struct console *co, char *options) |
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{ |
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struct efm32_uart_port *efm_port; |
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int baud = 115200; |
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int bits = 8; |
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int parity = 'n'; |
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int flow = 'n'; |
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int ret; |
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if (co->index < 0 || co->index >= ARRAY_SIZE(efm32_uart_ports)) { |
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unsigned i; |
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for (i = 0; i < ARRAY_SIZE(efm32_uart_ports); ++i) { |
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if (efm32_uart_ports[i]) { |
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pr_warn("efm32-console: fall back to console index %u (from %hhi)\n", |
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i, co->index); |
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co->index = i; |
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break; |
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} |
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} |
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} |
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efm_port = efm32_uart_ports[co->index]; |
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if (!efm_port) { |
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pr_warn("efm32-console: No port at %d\n", co->index); |
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return -ENODEV; |
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} |
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ret = clk_prepare(efm_port->clk); |
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if (ret) { |
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dev_warn(efm_port->port.dev, |
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"console: clk_prepare failed: %d\n", ret); |
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return ret; |
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} |
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|
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efm_port->port.uartclk = clk_get_rate(efm_port->clk); |
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if (options) |
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uart_parse_options(options, &baud, &parity, &bits, &flow); |
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else |
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efm32_uart_console_get_options(efm_port, |
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&baud, &parity, &bits); |
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return uart_set_options(&efm_port->port, co, baud, parity, bits, flow); |
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} |
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static struct uart_driver efm32_uart_reg; |
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|
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static struct console efm32_uart_console = { |
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.name = DEV_NAME, |
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.write = efm32_uart_console_write, |
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.device = uart_console_device, |
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.setup = efm32_uart_console_setup, |
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.flags = CON_PRINTBUFFER, |
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.index = -1, |
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.data = &efm32_uart_reg, |
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}; |
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#else |
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#define efm32_uart_console (*(struct console *)NULL) |
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#endif /* ifdef CONFIG_SERIAL_EFM32_UART_CONSOLE / else */ |
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static struct uart_driver efm32_uart_reg = { |
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.owner = THIS_MODULE, |
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.driver_name = DRIVER_NAME, |
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.dev_name = DEV_NAME, |
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.nr = ARRAY_SIZE(efm32_uart_ports), |
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.cons = &efm32_uart_console, |
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}; |
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|
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static int efm32_uart_probe_dt(struct platform_device *pdev, |
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struct efm32_uart_port *efm_port) |
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{ |
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struct device_node *np = pdev->dev.of_node; |
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u32 location; |
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int ret; |
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if (!np) |
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return 1; |
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ret = of_property_read_u32(np, "energymicro,location", &location); |
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if (ret) |
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/* fall back to wrongly namespaced property */ |
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ret = of_property_read_u32(np, "efm32,location", &location); |
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if (ret) |
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/* fall back to old and (wrongly) generic property "location" */ |
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ret = of_property_read_u32(np, "location", &location); |
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if (!ret) { |
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if (location > 5) { |
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dev_err(&pdev->dev, "invalid location\n"); |
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return -EINVAL; |
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} |
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efm_debug(efm_port, "using location %u\n", location); |
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efm_port->pdata.location = location; |
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} else { |
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efm_debug(efm_port, "fall back to location 0\n"); |
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} |
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ret = of_alias_get_id(np, "serial"); |
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if (ret < 0) { |
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dev_err(&pdev->dev, "failed to get alias id: %d\n", ret); |
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return ret; |
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} else { |
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efm_port->port.line = ret; |
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return 0; |
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} |
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} |
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static int efm32_uart_probe(struct platform_device *pdev) |
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{ |
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struct efm32_uart_port *efm_port; |
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struct resource *res; |
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unsigned int line; |
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int ret; |
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efm_port = kzalloc(sizeof(*efm_port), GFP_KERNEL); |
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if (!efm_port) { |
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dev_dbg(&pdev->dev, "failed to allocate private data\n"); |
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return -ENOMEM; |
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} |
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
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if (!res) { |
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ret = -ENODEV; |
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dev_dbg(&pdev->dev, "failed to determine base address\n"); |
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goto err_get_base; |
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} |
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if (resource_size(res) < 60) { |
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ret = -EINVAL; |
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dev_dbg(&pdev->dev, "memory resource too small\n"); |
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goto err_too_small; |
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} |
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ret = platform_get_irq(pdev, 0); |
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if (ret <= 0) { |
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dev_dbg(&pdev->dev, "failed to get rx irq\n"); |
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goto err_get_rxirq; |
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} |
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efm_port->port.irq = ret; |
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ret = platform_get_irq(pdev, 1); |
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if (ret <= 0) |
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ret = efm_port->port.irq + 1; |
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efm_port->txirq = ret; |
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efm_port->port.dev = &pdev->dev; |
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efm_port->port.mapbase = res->start; |
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efm_port->port.type = PORT_EFMUART; |
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efm_port->port.iotype = UPIO_MEM32; |
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efm_port->port.fifosize = 2; |
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efm_port->port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_EFM32_UART_CONSOLE); |
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efm_port->port.ops = &efm32_uart_pops; |
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efm_port->port.flags = UPF_BOOT_AUTOCONF; |
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ret = efm32_uart_probe_dt(pdev, efm_port); |
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if (ret > 0) { |
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/* not created by device tree */ |
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const struct efm32_uart_pdata *pdata = dev_get_platdata(&pdev->dev); |
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efm_port->port.line = pdev->id; |
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if (pdata) |
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efm_port->pdata = *pdata; |
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} else if (ret < 0) |
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goto err_probe_dt; |
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line = efm_port->port.line; |
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if (line >= 0 && line < ARRAY_SIZE(efm32_uart_ports)) |
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efm32_uart_ports[line] = efm_port; |
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ret = uart_add_one_port(&efm32_uart_reg, &efm_port->port); |
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if (ret) { |
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dev_dbg(&pdev->dev, "failed to add port: %d\n", ret); |
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if (line >= 0 && line < ARRAY_SIZE(efm32_uart_ports)) |
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efm32_uart_ports[line] = NULL; |
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err_probe_dt: |
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err_get_rxirq: |
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err_too_small: |
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err_get_base: |
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kfree(efm_port); |
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} else { |
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platform_set_drvdata(pdev, efm_port); |
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dev_dbg(&pdev->dev, "\\o/\n"); |
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} |
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return ret; |
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} |
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static int efm32_uart_remove(struct platform_device *pdev) |
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{ |
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struct efm32_uart_port *efm_port = platform_get_drvdata(pdev); |
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unsigned int line = efm_port->port.line; |
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uart_remove_one_port(&efm32_uart_reg, &efm_port->port); |
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if (line >= 0 && line < ARRAY_SIZE(efm32_uart_ports)) |
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efm32_uart_ports[line] = NULL; |
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kfree(efm_port); |
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return 0; |
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} |
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static const struct of_device_id efm32_uart_dt_ids[] = { |
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{ |
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.compatible = "energymicro,efm32-uart", |
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}, { |
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/* doesn't follow the "vendor,device" scheme, don't use */ |
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.compatible = "efm32,uart", |
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}, { |
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/* sentinel */ |
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} |
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}; |
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MODULE_DEVICE_TABLE(of, efm32_uart_dt_ids); |
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static struct platform_driver efm32_uart_driver = { |
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.probe = efm32_uart_probe, |
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.remove = efm32_uart_remove, |
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.driver = { |
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.name = DRIVER_NAME, |
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.of_match_table = efm32_uart_dt_ids, |
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}, |
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}; |
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static int __init efm32_uart_init(void) |
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{ |
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int ret; |
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ret = uart_register_driver(&efm32_uart_reg); |
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if (ret) |
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return ret; |
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ret = platform_driver_register(&efm32_uart_driver); |
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if (ret) |
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uart_unregister_driver(&efm32_uart_reg); |
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pr_info("EFM32 UART/USART driver\n"); |
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return ret; |
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} |
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module_init(efm32_uart_init); |
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static void __exit efm32_uart_exit(void) |
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{ |
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platform_driver_unregister(&efm32_uart_driver); |
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uart_unregister_driver(&efm32_uart_reg); |
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} |
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module_exit(efm32_uart_exit); |
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MODULE_AUTHOR("Uwe Kleine-Koenig <[email protected]>"); |
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MODULE_DESCRIPTION("EFM32 UART/USART driver"); |
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MODULE_LICENSE("GPL v2"); |
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MODULE_ALIAS("platform:" DRIVER_NAME);
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