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214 lines
5.5 KiB
214 lines
5.5 KiB
// SPDX-License-Identifier: GPL-2.0 |
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/* |
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* Serial port driver for NXP LPC18xx/43xx UART |
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* |
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* Copyright (C) 2015 Joachim Eastwood <[email protected]> |
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* |
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* Based on 8250_mtk.c: |
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* Copyright (c) 2014 MundoReader S.L. |
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* Matthias Brugger <[email protected]> |
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*/ |
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#include <linux/clk.h> |
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#include <linux/io.h> |
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#include <linux/module.h> |
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#include <linux/of.h> |
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#include <linux/platform_device.h> |
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#include "8250.h" |
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/* Additional LPC18xx/43xx 8250 registers and bits */ |
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#define LPC18XX_UART_RS485CTRL (0x04c / sizeof(u32)) |
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#define LPC18XX_UART_RS485CTRL_NMMEN BIT(0) |
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#define LPC18XX_UART_RS485CTRL_DCTRL BIT(4) |
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#define LPC18XX_UART_RS485CTRL_OINV BIT(5) |
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#define LPC18XX_UART_RS485DLY (0x054 / sizeof(u32)) |
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#define LPC18XX_UART_RS485DLY_MAX 255 |
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struct lpc18xx_uart_data { |
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struct uart_8250_dma dma; |
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struct clk *clk_uart; |
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struct clk *clk_reg; |
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int line; |
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}; |
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static int lpc18xx_rs485_config(struct uart_port *port, struct ktermios *termios, |
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struct serial_rs485 *rs485) |
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{ |
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struct uart_8250_port *up = up_to_u8250p(port); |
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u32 rs485_ctrl_reg = 0; |
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u32 rs485_dly_reg = 0; |
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unsigned baud_clk; |
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if (rs485->flags & SER_RS485_ENABLED) { |
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rs485_ctrl_reg |= LPC18XX_UART_RS485CTRL_NMMEN | |
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LPC18XX_UART_RS485CTRL_DCTRL; |
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if (rs485->flags & SER_RS485_RTS_ON_SEND) |
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rs485_ctrl_reg |= LPC18XX_UART_RS485CTRL_OINV; |
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} |
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if (rs485->delay_rts_after_send) { |
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baud_clk = port->uartclk / up->dl_read(up); |
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rs485_dly_reg = DIV_ROUND_UP(rs485->delay_rts_after_send |
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* baud_clk, MSEC_PER_SEC); |
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if (rs485_dly_reg > LPC18XX_UART_RS485DLY_MAX) |
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rs485_dly_reg = LPC18XX_UART_RS485DLY_MAX; |
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/* Calculate the resulting delay in ms */ |
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rs485->delay_rts_after_send = (rs485_dly_reg * MSEC_PER_SEC) |
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/ baud_clk; |
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} |
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serial_out(up, LPC18XX_UART_RS485CTRL, rs485_ctrl_reg); |
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serial_out(up, LPC18XX_UART_RS485DLY, rs485_dly_reg); |
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return 0; |
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} |
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static void lpc18xx_uart_serial_out(struct uart_port *p, int offset, int value) |
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{ |
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/* |
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* For DMA mode one must ensure that the UART_FCR_DMA_SELECT |
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* bit is set when FIFO is enabled. Even if DMA is not used |
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* setting this bit doesn't seem to affect anything. |
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*/ |
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if (offset == UART_FCR && (value & UART_FCR_ENABLE_FIFO)) |
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value |= UART_FCR_DMA_SELECT; |
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offset = offset << p->regshift; |
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writel(value, p->membase + offset); |
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} |
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static const struct serial_rs485 lpc18xx_rs485_supported = { |
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.flags = SER_RS485_ENABLED | SER_RS485_RTS_ON_SEND | SER_RS485_RTS_AFTER_SEND, |
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.delay_rts_after_send = 1, |
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/* Delay RTS before send is not supported */ |
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}; |
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static int lpc18xx_serial_probe(struct platform_device *pdev) |
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{ |
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struct lpc18xx_uart_data *data; |
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struct uart_8250_port uart; |
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struct resource *res; |
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int irq, ret; |
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irq = platform_get_irq(pdev, 0); |
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if (irq < 0) |
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return irq; |
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
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if (!res) { |
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dev_err(&pdev->dev, "memory resource not found"); |
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return -EINVAL; |
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} |
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memset(&uart, 0, sizeof(uart)); |
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uart.port.membase = devm_ioremap(&pdev->dev, res->start, |
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resource_size(res)); |
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if (!uart.port.membase) |
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return -ENOMEM; |
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data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL); |
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if (!data) |
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return -ENOMEM; |
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data->clk_uart = devm_clk_get(&pdev->dev, "uartclk"); |
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if (IS_ERR(data->clk_uart)) { |
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dev_err(&pdev->dev, "uart clock not found\n"); |
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return PTR_ERR(data->clk_uart); |
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} |
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data->clk_reg = devm_clk_get(&pdev->dev, "reg"); |
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if (IS_ERR(data->clk_reg)) { |
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dev_err(&pdev->dev, "reg clock not found\n"); |
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return PTR_ERR(data->clk_reg); |
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} |
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ret = clk_prepare_enable(data->clk_reg); |
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if (ret) { |
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dev_err(&pdev->dev, "unable to enable reg clock\n"); |
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return ret; |
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} |
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ret = clk_prepare_enable(data->clk_uart); |
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if (ret) { |
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dev_err(&pdev->dev, "unable to enable uart clock\n"); |
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goto dis_clk_reg; |
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} |
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ret = of_alias_get_id(pdev->dev.of_node, "serial"); |
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if (ret >= 0) |
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uart.port.line = ret; |
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data->dma.rx_param = data; |
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data->dma.tx_param = data; |
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spin_lock_init(&uart.port.lock); |
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uart.port.dev = &pdev->dev; |
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uart.port.irq = irq; |
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uart.port.iotype = UPIO_MEM32; |
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uart.port.mapbase = res->start; |
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uart.port.regshift = 2; |
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uart.port.type = PORT_16550A; |
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uart.port.flags = UPF_FIXED_PORT | UPF_FIXED_TYPE | UPF_SKIP_TEST; |
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uart.port.uartclk = clk_get_rate(data->clk_uart); |
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uart.port.private_data = data; |
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uart.port.rs485_config = lpc18xx_rs485_config; |
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uart.port.rs485_supported = lpc18xx_rs485_supported; |
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uart.port.serial_out = lpc18xx_uart_serial_out; |
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uart.dma = &data->dma; |
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uart.dma->rxconf.src_maxburst = 1; |
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uart.dma->txconf.dst_maxburst = 1; |
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ret = serial8250_register_8250_port(&uart); |
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if (ret < 0) { |
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dev_err(&pdev->dev, "unable to register 8250 port\n"); |
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goto dis_uart_clk; |
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} |
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data->line = ret; |
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platform_set_drvdata(pdev, data); |
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return 0; |
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dis_uart_clk: |
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clk_disable_unprepare(data->clk_uart); |
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dis_clk_reg: |
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clk_disable_unprepare(data->clk_reg); |
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return ret; |
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} |
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static int lpc18xx_serial_remove(struct platform_device *pdev) |
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{ |
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struct lpc18xx_uart_data *data = platform_get_drvdata(pdev); |
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serial8250_unregister_port(data->line); |
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clk_disable_unprepare(data->clk_uart); |
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clk_disable_unprepare(data->clk_reg); |
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return 0; |
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} |
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static const struct of_device_id lpc18xx_serial_match[] = { |
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{ .compatible = "nxp,lpc1850-uart" }, |
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{ }, |
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}; |
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MODULE_DEVICE_TABLE(of, lpc18xx_serial_match); |
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static struct platform_driver lpc18xx_serial_driver = { |
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.probe = lpc18xx_serial_probe, |
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.remove = lpc18xx_serial_remove, |
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.driver = { |
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.name = "lpc18xx-uart", |
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.of_match_table = lpc18xx_serial_match, |
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}, |
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}; |
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module_platform_driver(lpc18xx_serial_driver); |
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MODULE_AUTHOR("Joachim Eastwood <[email protected]>"); |
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MODULE_DESCRIPTION("Serial port driver NXP LPC18xx/43xx devices"); |
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MODULE_LICENSE("GPL v2");
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