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201 lines
5.0 KiB
201 lines
5.0 KiB
/* |
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* Sonics Silicon Backplane |
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* Broadcom EXTIF core driver |
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* |
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* Copyright 2005, Broadcom Corporation |
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* Copyright 2006, 2007, Michael Buesch <[email protected]> |
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* Copyright 2006, 2007, Felix Fietkau <[email protected]> |
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* Copyright 2007, Aurelien Jarno <[email protected]> |
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* |
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* Licensed under the GNU/GPL. See COPYING for details. |
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*/ |
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#include "ssb_private.h" |
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#include <linux/serial.h> |
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#include <linux/serial_core.h> |
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#include <linux/serial_reg.h> |
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static inline u32 extif_read32(struct ssb_extif *extif, u16 offset) |
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{ |
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return ssb_read32(extif->dev, offset); |
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} |
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static inline void extif_write32(struct ssb_extif *extif, u16 offset, u32 value) |
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{ |
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ssb_write32(extif->dev, offset, value); |
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} |
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static inline u32 extif_write32_masked(struct ssb_extif *extif, u16 offset, |
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u32 mask, u32 value) |
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{ |
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value &= mask; |
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value |= extif_read32(extif, offset) & ~mask; |
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extif_write32(extif, offset, value); |
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return value; |
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} |
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#ifdef CONFIG_SSB_SERIAL |
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static bool serial_exists(u8 *regs) |
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{ |
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u8 save_mcr, msr = 0; |
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if (regs) { |
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save_mcr = regs[UART_MCR]; |
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regs[UART_MCR] = (UART_MCR_LOOP | UART_MCR_OUT2 | UART_MCR_RTS); |
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msr = regs[UART_MSR] & (UART_MSR_DCD | UART_MSR_RI |
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| UART_MSR_CTS | UART_MSR_DSR); |
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regs[UART_MCR] = save_mcr; |
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} |
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return (msr == (UART_MSR_DCD | UART_MSR_CTS)); |
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} |
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int ssb_extif_serial_init(struct ssb_extif *extif, struct ssb_serial_port *ports) |
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{ |
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u32 i, nr_ports = 0; |
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/* Disable GPIO interrupt initially */ |
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extif_write32(extif, SSB_EXTIF_GPIO_INTPOL, 0); |
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extif_write32(extif, SSB_EXTIF_GPIO_INTMASK, 0); |
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for (i = 0; i < 2; i++) { |
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void __iomem *uart_regs; |
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uart_regs = ioremap(SSB_EUART, 16); |
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if (uart_regs) { |
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uart_regs += (i * 8); |
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if (serial_exists(uart_regs) && ports) { |
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extif_write32(extif, SSB_EXTIF_GPIO_INTMASK, 2); |
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nr_ports++; |
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ports[i].regs = uart_regs; |
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ports[i].irq = 2; |
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ports[i].baud_base = 13500000; |
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ports[i].reg_shift = 0; |
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} |
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iounmap(uart_regs); |
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} |
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} |
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return nr_ports; |
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} |
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#endif /* CONFIG_SSB_SERIAL */ |
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void ssb_extif_timing_init(struct ssb_extif *extif, unsigned long ns) |
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{ |
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u32 tmp; |
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/* Initialize extif so we can get to the LEDs and external UART */ |
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extif_write32(extif, SSB_EXTIF_PROG_CFG, SSB_EXTCFG_EN); |
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/* Set timing for the flash */ |
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tmp = DIV_ROUND_UP(10, ns) << SSB_PROG_WCNT_3_SHIFT; |
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tmp |= DIV_ROUND_UP(40, ns) << SSB_PROG_WCNT_1_SHIFT; |
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tmp |= DIV_ROUND_UP(120, ns); |
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extif_write32(extif, SSB_EXTIF_PROG_WAITCNT, tmp); |
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/* Set programmable interface timing for external uart */ |
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tmp = DIV_ROUND_UP(10, ns) << SSB_PROG_WCNT_3_SHIFT; |
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tmp |= DIV_ROUND_UP(20, ns) << SSB_PROG_WCNT_2_SHIFT; |
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tmp |= DIV_ROUND_UP(100, ns) << SSB_PROG_WCNT_1_SHIFT; |
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tmp |= DIV_ROUND_UP(120, ns); |
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extif_write32(extif, SSB_EXTIF_PROG_WAITCNT, tmp); |
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} |
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void ssb_extif_get_clockcontrol(struct ssb_extif *extif, |
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u32 *pll_type, u32 *n, u32 *m) |
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{ |
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*pll_type = SSB_PLLTYPE_1; |
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*n = extif_read32(extif, SSB_EXTIF_CLOCK_N); |
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*m = extif_read32(extif, SSB_EXTIF_CLOCK_SB); |
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} |
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u32 ssb_extif_watchdog_timer_set_wdt(struct bcm47xx_wdt *wdt, u32 ticks) |
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{ |
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struct ssb_extif *extif = bcm47xx_wdt_get_drvdata(wdt); |
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return ssb_extif_watchdog_timer_set(extif, ticks); |
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} |
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u32 ssb_extif_watchdog_timer_set_ms(struct bcm47xx_wdt *wdt, u32 ms) |
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{ |
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struct ssb_extif *extif = bcm47xx_wdt_get_drvdata(wdt); |
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u32 ticks = (SSB_EXTIF_WATCHDOG_CLK / 1000) * ms; |
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ticks = ssb_extif_watchdog_timer_set(extif, ticks); |
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return (ticks * 1000) / SSB_EXTIF_WATCHDOG_CLK; |
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} |
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u32 ssb_extif_watchdog_timer_set(struct ssb_extif *extif, u32 ticks) |
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{ |
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if (ticks > SSB_EXTIF_WATCHDOG_MAX_TIMER) |
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ticks = SSB_EXTIF_WATCHDOG_MAX_TIMER; |
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extif_write32(extif, SSB_EXTIF_WATCHDOG, ticks); |
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return ticks; |
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} |
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void ssb_extif_init(struct ssb_extif *extif) |
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{ |
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if (!extif->dev) |
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return; /* We don't have a Extif core */ |
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spin_lock_init(&extif->gpio_lock); |
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} |
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u32 ssb_extif_gpio_in(struct ssb_extif *extif, u32 mask) |
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{ |
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return extif_read32(extif, SSB_EXTIF_GPIO_IN) & mask; |
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} |
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u32 ssb_extif_gpio_out(struct ssb_extif *extif, u32 mask, u32 value) |
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{ |
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unsigned long flags; |
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u32 res = 0; |
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spin_lock_irqsave(&extif->gpio_lock, flags); |
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res = extif_write32_masked(extif, SSB_EXTIF_GPIO_OUT(0), |
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mask, value); |
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spin_unlock_irqrestore(&extif->gpio_lock, flags); |
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return res; |
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} |
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u32 ssb_extif_gpio_outen(struct ssb_extif *extif, u32 mask, u32 value) |
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{ |
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unsigned long flags; |
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u32 res = 0; |
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spin_lock_irqsave(&extif->gpio_lock, flags); |
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res = extif_write32_masked(extif, SSB_EXTIF_GPIO_OUTEN(0), |
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mask, value); |
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spin_unlock_irqrestore(&extif->gpio_lock, flags); |
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return res; |
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} |
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u32 ssb_extif_gpio_polarity(struct ssb_extif *extif, u32 mask, u32 value) |
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{ |
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unsigned long flags; |
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u32 res = 0; |
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spin_lock_irqsave(&extif->gpio_lock, flags); |
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res = extif_write32_masked(extif, SSB_EXTIF_GPIO_INTPOL, mask, value); |
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spin_unlock_irqrestore(&extif->gpio_lock, flags); |
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return res; |
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} |
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u32 ssb_extif_gpio_intmask(struct ssb_extif *extif, u32 mask, u32 value) |
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{ |
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unsigned long flags; |
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u32 res = 0; |
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spin_lock_irqsave(&extif->gpio_lock, flags); |
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res = extif_write32_masked(extif, SSB_EXTIF_GPIO_INTMASK, mask, value); |
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spin_unlock_irqrestore(&extif->gpio_lock, flags); |
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return res; |
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}
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