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873 lines
24 KiB
873 lines
24 KiB
// SPDX-License-Identifier: GPL-2.0+ |
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/* |
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* Copyright 2021 Pengutronix, Lucas Stach <[email protected]> |
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*/ |
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#include <linux/device.h> |
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#include <linux/interconnect.h> |
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#include <linux/module.h> |
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#include <linux/of_device.h> |
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#include <linux/platform_device.h> |
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#include <linux/pm_domain.h> |
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#include <linux/pm_runtime.h> |
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#include <linux/regmap.h> |
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#include <linux/clk.h> |
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#include <dt-bindings/power/imx8mm-power.h> |
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#include <dt-bindings/power/imx8mn-power.h> |
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#include <dt-bindings/power/imx8mp-power.h> |
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#include <dt-bindings/power/imx8mq-power.h> |
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#define BLK_SFT_RSTN 0x0 |
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#define BLK_CLK_EN 0x4 |
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#define BLK_MIPI_RESET_DIV 0x8 /* Mini/Nano/Plus DISPLAY_BLK_CTRL only */ |
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struct imx8m_blk_ctrl_domain; |
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struct imx8m_blk_ctrl { |
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struct device *dev; |
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struct notifier_block power_nb; |
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struct device *bus_power_dev; |
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struct regmap *regmap; |
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struct imx8m_blk_ctrl_domain *domains; |
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struct genpd_onecell_data onecell_data; |
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}; |
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struct imx8m_blk_ctrl_domain_data { |
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const char *name; |
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const char * const *clk_names; |
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int num_clks; |
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const char * const *path_names; |
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int num_paths; |
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const char *gpc_name; |
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u32 rst_mask; |
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u32 clk_mask; |
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/* |
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* i.MX8M Mini, Nano and Plus have a third DISPLAY_BLK_CTRL register |
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* which is used to control the reset for the MIPI Phy. |
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* Since it's only present in certain circumstances, |
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* an if-statement should be used before setting and clearing this |
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* register. |
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*/ |
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u32 mipi_phy_rst_mask; |
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}; |
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#define DOMAIN_MAX_CLKS 4 |
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#define DOMAIN_MAX_PATHS 4 |
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struct imx8m_blk_ctrl_domain { |
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struct generic_pm_domain genpd; |
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const struct imx8m_blk_ctrl_domain_data *data; |
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struct clk_bulk_data clks[DOMAIN_MAX_CLKS]; |
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struct icc_bulk_data paths[DOMAIN_MAX_PATHS]; |
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struct device *power_dev; |
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struct imx8m_blk_ctrl *bc; |
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int num_paths; |
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}; |
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struct imx8m_blk_ctrl_data { |
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int max_reg; |
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notifier_fn_t power_notifier_fn; |
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const struct imx8m_blk_ctrl_domain_data *domains; |
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int num_domains; |
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}; |
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static inline struct imx8m_blk_ctrl_domain * |
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to_imx8m_blk_ctrl_domain(struct generic_pm_domain *genpd) |
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{ |
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return container_of(genpd, struct imx8m_blk_ctrl_domain, genpd); |
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} |
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static int imx8m_blk_ctrl_power_on(struct generic_pm_domain *genpd) |
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{ |
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struct imx8m_blk_ctrl_domain *domain = to_imx8m_blk_ctrl_domain(genpd); |
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const struct imx8m_blk_ctrl_domain_data *data = domain->data; |
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struct imx8m_blk_ctrl *bc = domain->bc; |
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int ret; |
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/* make sure bus domain is awake */ |
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ret = pm_runtime_get_sync(bc->bus_power_dev); |
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if (ret < 0) { |
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pm_runtime_put_noidle(bc->bus_power_dev); |
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dev_err(bc->dev, "failed to power up bus domain\n"); |
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return ret; |
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} |
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/* put devices into reset */ |
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regmap_clear_bits(bc->regmap, BLK_SFT_RSTN, data->rst_mask); |
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if (data->mipi_phy_rst_mask) |
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regmap_clear_bits(bc->regmap, BLK_MIPI_RESET_DIV, data->mipi_phy_rst_mask); |
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/* enable upstream and blk-ctrl clocks to allow reset to propagate */ |
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ret = clk_bulk_prepare_enable(data->num_clks, domain->clks); |
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if (ret) { |
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dev_err(bc->dev, "failed to enable clocks\n"); |
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goto bus_put; |
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} |
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regmap_set_bits(bc->regmap, BLK_CLK_EN, data->clk_mask); |
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/* power up upstream GPC domain */ |
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ret = pm_runtime_get_sync(domain->power_dev); |
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if (ret < 0) { |
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dev_err(bc->dev, "failed to power up peripheral domain\n"); |
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goto clk_disable; |
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} |
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/* wait for reset to propagate */ |
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udelay(5); |
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/* release reset */ |
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regmap_set_bits(bc->regmap, BLK_SFT_RSTN, data->rst_mask); |
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if (data->mipi_phy_rst_mask) |
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regmap_set_bits(bc->regmap, BLK_MIPI_RESET_DIV, data->mipi_phy_rst_mask); |
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ret = icc_bulk_set_bw(domain->num_paths, domain->paths); |
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if (ret) |
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dev_err(bc->dev, "failed to set icc bw\n"); |
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/* disable upstream clocks */ |
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clk_bulk_disable_unprepare(data->num_clks, domain->clks); |
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return 0; |
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clk_disable: |
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clk_bulk_disable_unprepare(data->num_clks, domain->clks); |
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bus_put: |
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pm_runtime_put(bc->bus_power_dev); |
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return ret; |
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} |
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static int imx8m_blk_ctrl_power_off(struct generic_pm_domain *genpd) |
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{ |
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struct imx8m_blk_ctrl_domain *domain = to_imx8m_blk_ctrl_domain(genpd); |
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const struct imx8m_blk_ctrl_domain_data *data = domain->data; |
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struct imx8m_blk_ctrl *bc = domain->bc; |
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/* put devices into reset and disable clocks */ |
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if (data->mipi_phy_rst_mask) |
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regmap_clear_bits(bc->regmap, BLK_MIPI_RESET_DIV, data->mipi_phy_rst_mask); |
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regmap_clear_bits(bc->regmap, BLK_SFT_RSTN, data->rst_mask); |
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regmap_clear_bits(bc->regmap, BLK_CLK_EN, data->clk_mask); |
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/* power down upstream GPC domain */ |
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pm_runtime_put(domain->power_dev); |
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/* allow bus domain to suspend */ |
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pm_runtime_put(bc->bus_power_dev); |
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return 0; |
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} |
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static struct lock_class_key blk_ctrl_genpd_lock_class; |
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static int imx8m_blk_ctrl_probe(struct platform_device *pdev) |
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{ |
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const struct imx8m_blk_ctrl_data *bc_data; |
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struct device *dev = &pdev->dev; |
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struct imx8m_blk_ctrl *bc; |
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void __iomem *base; |
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int i, ret; |
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struct regmap_config regmap_config = { |
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.reg_bits = 32, |
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.val_bits = 32, |
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.reg_stride = 4, |
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}; |
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bc = devm_kzalloc(dev, sizeof(*bc), GFP_KERNEL); |
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if (!bc) |
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return -ENOMEM; |
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bc->dev = dev; |
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bc_data = of_device_get_match_data(dev); |
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base = devm_platform_ioremap_resource(pdev, 0); |
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if (IS_ERR(base)) |
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return PTR_ERR(base); |
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regmap_config.max_register = bc_data->max_reg; |
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bc->regmap = devm_regmap_init_mmio(dev, base, ®map_config); |
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if (IS_ERR(bc->regmap)) |
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return dev_err_probe(dev, PTR_ERR(bc->regmap), |
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"failed to init regmap\n"); |
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bc->domains = devm_kcalloc(dev, bc_data->num_domains, |
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sizeof(struct imx8m_blk_ctrl_domain), |
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GFP_KERNEL); |
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if (!bc->domains) |
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return -ENOMEM; |
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bc->onecell_data.num_domains = bc_data->num_domains; |
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bc->onecell_data.domains = |
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devm_kcalloc(dev, bc_data->num_domains, |
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sizeof(struct generic_pm_domain *), GFP_KERNEL); |
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if (!bc->onecell_data.domains) |
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return -ENOMEM; |
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bc->bus_power_dev = genpd_dev_pm_attach_by_name(dev, "bus"); |
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if (IS_ERR(bc->bus_power_dev)) |
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return dev_err_probe(dev, PTR_ERR(bc->bus_power_dev), |
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"failed to attach power domain \"bus\"\n"); |
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for (i = 0; i < bc_data->num_domains; i++) { |
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const struct imx8m_blk_ctrl_domain_data *data = &bc_data->domains[i]; |
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struct imx8m_blk_ctrl_domain *domain = &bc->domains[i]; |
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int j; |
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domain->data = data; |
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domain->num_paths = data->num_paths; |
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for (j = 0; j < data->num_clks; j++) |
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domain->clks[j].id = data->clk_names[j]; |
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for (j = 0; j < data->num_paths; j++) { |
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domain->paths[j].name = data->path_names[j]; |
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/* Fake value for now, just let ICC could configure NoC mode/priority */ |
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domain->paths[j].avg_bw = 1; |
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domain->paths[j].peak_bw = 1; |
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} |
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ret = devm_of_icc_bulk_get(dev, data->num_paths, domain->paths); |
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if (ret) { |
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if (ret != -EPROBE_DEFER) { |
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dev_warn_once(dev, "Could not get interconnect paths, NoC will stay unconfigured!\n"); |
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domain->num_paths = 0; |
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} else { |
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dev_err_probe(dev, ret, "failed to get noc entries\n"); |
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goto cleanup_pds; |
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} |
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} |
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ret = devm_clk_bulk_get(dev, data->num_clks, domain->clks); |
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if (ret) { |
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dev_err_probe(dev, ret, "failed to get clock\n"); |
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goto cleanup_pds; |
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} |
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domain->power_dev = |
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dev_pm_domain_attach_by_name(dev, data->gpc_name); |
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if (IS_ERR(domain->power_dev)) { |
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dev_err_probe(dev, PTR_ERR(domain->power_dev), |
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"failed to attach power domain \"%s\"\n", |
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data->gpc_name); |
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ret = PTR_ERR(domain->power_dev); |
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goto cleanup_pds; |
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} |
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domain->genpd.name = data->name; |
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domain->genpd.power_on = imx8m_blk_ctrl_power_on; |
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domain->genpd.power_off = imx8m_blk_ctrl_power_off; |
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domain->bc = bc; |
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ret = pm_genpd_init(&domain->genpd, NULL, true); |
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if (ret) { |
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dev_err_probe(dev, ret, |
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"failed to init power domain \"%s\"\n", |
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data->gpc_name); |
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dev_pm_domain_detach(domain->power_dev, true); |
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goto cleanup_pds; |
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} |
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/* |
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* We use runtime PM to trigger power on/off of the upstream GPC |
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* domain, as a strict hierarchical parent/child power domain |
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* setup doesn't allow us to meet the sequencing requirements. |
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* This means we have nested locking of genpd locks, without the |
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* nesting being visible at the genpd level, so we need a |
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* separate lock class to make lockdep aware of the fact that |
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* this are separate domain locks that can be nested without a |
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* self-deadlock. |
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*/ |
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lockdep_set_class(&domain->genpd.mlock, |
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&blk_ctrl_genpd_lock_class); |
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bc->onecell_data.domains[i] = &domain->genpd; |
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} |
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ret = of_genpd_add_provider_onecell(dev->of_node, &bc->onecell_data); |
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if (ret) { |
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dev_err_probe(dev, ret, "failed to add power domain provider\n"); |
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goto cleanup_pds; |
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} |
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bc->power_nb.notifier_call = bc_data->power_notifier_fn; |
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ret = dev_pm_genpd_add_notifier(bc->bus_power_dev, &bc->power_nb); |
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if (ret) { |
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dev_err_probe(dev, ret, "failed to add power notifier\n"); |
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goto cleanup_provider; |
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} |
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dev_set_drvdata(dev, bc); |
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return 0; |
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cleanup_provider: |
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of_genpd_del_provider(dev->of_node); |
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cleanup_pds: |
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for (i--; i >= 0; i--) { |
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pm_genpd_remove(&bc->domains[i].genpd); |
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dev_pm_domain_detach(bc->domains[i].power_dev, true); |
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} |
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dev_pm_domain_detach(bc->bus_power_dev, true); |
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return ret; |
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} |
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static int imx8m_blk_ctrl_remove(struct platform_device *pdev) |
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{ |
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struct imx8m_blk_ctrl *bc = dev_get_drvdata(&pdev->dev); |
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int i; |
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of_genpd_del_provider(pdev->dev.of_node); |
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for (i = 0; bc->onecell_data.num_domains; i++) { |
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struct imx8m_blk_ctrl_domain *domain = &bc->domains[i]; |
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pm_genpd_remove(&domain->genpd); |
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dev_pm_domain_detach(domain->power_dev, true); |
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} |
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dev_pm_genpd_remove_notifier(bc->bus_power_dev); |
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dev_pm_domain_detach(bc->bus_power_dev, true); |
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return 0; |
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} |
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#ifdef CONFIG_PM_SLEEP |
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static int imx8m_blk_ctrl_suspend(struct device *dev) |
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{ |
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struct imx8m_blk_ctrl *bc = dev_get_drvdata(dev); |
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int ret, i; |
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/* |
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* This may look strange, but is done so the generic PM_SLEEP code |
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* can power down our domains and more importantly power them up again |
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* after resume, without tripping over our usage of runtime PM to |
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* control the upstream GPC domains. Things happen in the right order |
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* in the system suspend/resume paths due to the device parent/child |
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* hierarchy. |
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*/ |
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ret = pm_runtime_get_sync(bc->bus_power_dev); |
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if (ret < 0) { |
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pm_runtime_put_noidle(bc->bus_power_dev); |
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return ret; |
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} |
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for (i = 0; i < bc->onecell_data.num_domains; i++) { |
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struct imx8m_blk_ctrl_domain *domain = &bc->domains[i]; |
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ret = pm_runtime_get_sync(domain->power_dev); |
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if (ret < 0) { |
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pm_runtime_put_noidle(domain->power_dev); |
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goto out_fail; |
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} |
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} |
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return 0; |
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out_fail: |
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for (i--; i >= 0; i--) |
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pm_runtime_put(bc->domains[i].power_dev); |
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pm_runtime_put(bc->bus_power_dev); |
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return ret; |
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} |
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static int imx8m_blk_ctrl_resume(struct device *dev) |
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{ |
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struct imx8m_blk_ctrl *bc = dev_get_drvdata(dev); |
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int i; |
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for (i = 0; i < bc->onecell_data.num_domains; i++) |
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pm_runtime_put(bc->domains[i].power_dev); |
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pm_runtime_put(bc->bus_power_dev); |
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return 0; |
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} |
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#endif |
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static const struct dev_pm_ops imx8m_blk_ctrl_pm_ops = { |
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SET_SYSTEM_SLEEP_PM_OPS(imx8m_blk_ctrl_suspend, imx8m_blk_ctrl_resume) |
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}; |
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static int imx8mm_vpu_power_notifier(struct notifier_block *nb, |
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unsigned long action, void *data) |
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{ |
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struct imx8m_blk_ctrl *bc = container_of(nb, struct imx8m_blk_ctrl, |
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power_nb); |
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if (action != GENPD_NOTIFY_ON && action != GENPD_NOTIFY_PRE_OFF) |
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return NOTIFY_OK; |
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/* |
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* The ADB in the VPUMIX domain has no separate reset and clock |
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* enable bits, but is ungated together with the VPU clocks. To |
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* allow the handshake with the GPC to progress we put the VPUs |
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* in reset and ungate the clocks. |
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*/ |
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regmap_clear_bits(bc->regmap, BLK_SFT_RSTN, BIT(0) | BIT(1) | BIT(2)); |
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regmap_set_bits(bc->regmap, BLK_CLK_EN, BIT(0) | BIT(1) | BIT(2)); |
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if (action == GENPD_NOTIFY_ON) { |
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/* |
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* On power up we have no software backchannel to the GPC to |
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* wait for the ADB handshake to happen, so we just delay for a |
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* bit. On power down the GPC driver waits for the handshake. |
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*/ |
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udelay(5); |
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/* set "fuse" bits to enable the VPUs */ |
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regmap_set_bits(bc->regmap, 0x8, 0xffffffff); |
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regmap_set_bits(bc->regmap, 0xc, 0xffffffff); |
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regmap_set_bits(bc->regmap, 0x10, 0xffffffff); |
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regmap_set_bits(bc->regmap, 0x14, 0xffffffff); |
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} |
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return NOTIFY_OK; |
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} |
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static const struct imx8m_blk_ctrl_domain_data imx8mm_vpu_blk_ctl_domain_data[] = { |
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[IMX8MM_VPUBLK_PD_G1] = { |
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.name = "vpublk-g1", |
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.clk_names = (const char *[]){ "g1", }, |
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.num_clks = 1, |
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.gpc_name = "g1", |
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.rst_mask = BIT(1), |
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.clk_mask = BIT(1), |
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}, |
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[IMX8MM_VPUBLK_PD_G2] = { |
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.name = "vpublk-g2", |
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.clk_names = (const char *[]){ "g2", }, |
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.num_clks = 1, |
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.gpc_name = "g2", |
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.rst_mask = BIT(0), |
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.clk_mask = BIT(0), |
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}, |
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[IMX8MM_VPUBLK_PD_H1] = { |
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.name = "vpublk-h1", |
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.clk_names = (const char *[]){ "h1", }, |
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.num_clks = 1, |
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.gpc_name = "h1", |
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.rst_mask = BIT(2), |
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.clk_mask = BIT(2), |
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}, |
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}; |
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static const struct imx8m_blk_ctrl_data imx8mm_vpu_blk_ctl_dev_data = { |
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.max_reg = 0x18, |
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.power_notifier_fn = imx8mm_vpu_power_notifier, |
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.domains = imx8mm_vpu_blk_ctl_domain_data, |
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.num_domains = ARRAY_SIZE(imx8mm_vpu_blk_ctl_domain_data), |
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}; |
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static const struct imx8m_blk_ctrl_domain_data imx8mp_vpu_blk_ctl_domain_data[] = { |
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[IMX8MP_VPUBLK_PD_G1] = { |
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.name = "vpublk-g1", |
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.clk_names = (const char *[]){ "g1", }, |
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.num_clks = 1, |
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.gpc_name = "g1", |
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.rst_mask = BIT(1), |
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.clk_mask = BIT(1), |
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.path_names = (const char *[]){"g1"}, |
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.num_paths = 1, |
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}, |
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[IMX8MP_VPUBLK_PD_G2] = { |
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.name = "vpublk-g2", |
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.clk_names = (const char *[]){ "g2", }, |
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.num_clks = 1, |
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.gpc_name = "g2", |
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.rst_mask = BIT(0), |
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.clk_mask = BIT(0), |
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.path_names = (const char *[]){"g2"}, |
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.num_paths = 1, |
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}, |
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[IMX8MP_VPUBLK_PD_VC8000E] = { |
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.name = "vpublk-vc8000e", |
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.clk_names = (const char *[]){ "vc8000e", }, |
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.num_clks = 1, |
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.gpc_name = "vc8000e", |
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.rst_mask = BIT(2), |
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.clk_mask = BIT(2), |
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.path_names = (const char *[]){"vc8000e"}, |
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.num_paths = 1, |
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}, |
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}; |
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static const struct imx8m_blk_ctrl_data imx8mp_vpu_blk_ctl_dev_data = { |
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.max_reg = 0x18, |
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.power_notifier_fn = imx8mm_vpu_power_notifier, |
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.domains = imx8mp_vpu_blk_ctl_domain_data, |
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.num_domains = ARRAY_SIZE(imx8mp_vpu_blk_ctl_domain_data), |
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}; |
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static int imx8mm_disp_power_notifier(struct notifier_block *nb, |
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unsigned long action, void *data) |
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{ |
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struct imx8m_blk_ctrl *bc = container_of(nb, struct imx8m_blk_ctrl, |
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power_nb); |
|
|
|
if (action != GENPD_NOTIFY_ON && action != GENPD_NOTIFY_PRE_OFF) |
|
return NOTIFY_OK; |
|
|
|
/* Enable bus clock and deassert bus reset */ |
|
regmap_set_bits(bc->regmap, BLK_CLK_EN, BIT(12)); |
|
regmap_set_bits(bc->regmap, BLK_SFT_RSTN, BIT(6)); |
|
|
|
/* |
|
* On power up we have no software backchannel to the GPC to |
|
* wait for the ADB handshake to happen, so we just delay for a |
|
* bit. On power down the GPC driver waits for the handshake. |
|
*/ |
|
if (action == GENPD_NOTIFY_ON) |
|
udelay(5); |
|
|
|
|
|
return NOTIFY_OK; |
|
} |
|
|
|
static const struct imx8m_blk_ctrl_domain_data imx8mm_disp_blk_ctl_domain_data[] = { |
|
[IMX8MM_DISPBLK_PD_CSI_BRIDGE] = { |
|
.name = "dispblk-csi-bridge", |
|
.clk_names = (const char *[]){ "csi-bridge-axi", "csi-bridge-apb", |
|
"csi-bridge-core", }, |
|
.num_clks = 3, |
|
.gpc_name = "csi-bridge", |
|
.rst_mask = BIT(0) | BIT(1) | BIT(2), |
|
.clk_mask = BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(5), |
|
}, |
|
[IMX8MM_DISPBLK_PD_LCDIF] = { |
|
.name = "dispblk-lcdif", |
|
.clk_names = (const char *[]){ "lcdif-axi", "lcdif-apb", "lcdif-pix", }, |
|
.num_clks = 3, |
|
.gpc_name = "lcdif", |
|
.clk_mask = BIT(6) | BIT(7), |
|
}, |
|
[IMX8MM_DISPBLK_PD_MIPI_DSI] = { |
|
.name = "dispblk-mipi-dsi", |
|
.clk_names = (const char *[]){ "dsi-pclk", "dsi-ref", }, |
|
.num_clks = 2, |
|
.gpc_name = "mipi-dsi", |
|
.rst_mask = BIT(5), |
|
.clk_mask = BIT(8) | BIT(9), |
|
.mipi_phy_rst_mask = BIT(17), |
|
}, |
|
[IMX8MM_DISPBLK_PD_MIPI_CSI] = { |
|
.name = "dispblk-mipi-csi", |
|
.clk_names = (const char *[]){ "csi-aclk", "csi-pclk" }, |
|
.num_clks = 2, |
|
.gpc_name = "mipi-csi", |
|
.rst_mask = BIT(3) | BIT(4), |
|
.clk_mask = BIT(10) | BIT(11), |
|
.mipi_phy_rst_mask = BIT(16), |
|
}, |
|
}; |
|
|
|
static const struct imx8m_blk_ctrl_data imx8mm_disp_blk_ctl_dev_data = { |
|
.max_reg = 0x2c, |
|
.power_notifier_fn = imx8mm_disp_power_notifier, |
|
.domains = imx8mm_disp_blk_ctl_domain_data, |
|
.num_domains = ARRAY_SIZE(imx8mm_disp_blk_ctl_domain_data), |
|
}; |
|
|
|
|
|
static int imx8mn_disp_power_notifier(struct notifier_block *nb, |
|
unsigned long action, void *data) |
|
{ |
|
struct imx8m_blk_ctrl *bc = container_of(nb, struct imx8m_blk_ctrl, |
|
power_nb); |
|
|
|
if (action != GENPD_NOTIFY_ON && action != GENPD_NOTIFY_PRE_OFF) |
|
return NOTIFY_OK; |
|
|
|
/* Enable bus clock and deassert bus reset */ |
|
regmap_set_bits(bc->regmap, BLK_CLK_EN, BIT(8)); |
|
regmap_set_bits(bc->regmap, BLK_SFT_RSTN, BIT(8)); |
|
|
|
/* |
|
* On power up we have no software backchannel to the GPC to |
|
* wait for the ADB handshake to happen, so we just delay for a |
|
* bit. On power down the GPC driver waits for the handshake. |
|
*/ |
|
if (action == GENPD_NOTIFY_ON) |
|
udelay(5); |
|
|
|
|
|
return NOTIFY_OK; |
|
} |
|
|
|
static const struct imx8m_blk_ctrl_domain_data imx8mn_disp_blk_ctl_domain_data[] = { |
|
[IMX8MN_DISPBLK_PD_MIPI_DSI] = { |
|
.name = "dispblk-mipi-dsi", |
|
.clk_names = (const char *[]){ "dsi-pclk", "dsi-ref", }, |
|
.num_clks = 2, |
|
.gpc_name = "mipi-dsi", |
|
.rst_mask = BIT(0) | BIT(1), |
|
.clk_mask = BIT(0) | BIT(1), |
|
.mipi_phy_rst_mask = BIT(17), |
|
}, |
|
[IMX8MN_DISPBLK_PD_MIPI_CSI] = { |
|
.name = "dispblk-mipi-csi", |
|
.clk_names = (const char *[]){ "csi-aclk", "csi-pclk" }, |
|
.num_clks = 2, |
|
.gpc_name = "mipi-csi", |
|
.rst_mask = BIT(2) | BIT(3), |
|
.clk_mask = BIT(2) | BIT(3), |
|
.mipi_phy_rst_mask = BIT(16), |
|
}, |
|
[IMX8MN_DISPBLK_PD_LCDIF] = { |
|
.name = "dispblk-lcdif", |
|
.clk_names = (const char *[]){ "lcdif-axi", "lcdif-apb", "lcdif-pix", }, |
|
.num_clks = 3, |
|
.gpc_name = "lcdif", |
|
.rst_mask = BIT(4) | BIT(5), |
|
.clk_mask = BIT(4) | BIT(5), |
|
}, |
|
[IMX8MN_DISPBLK_PD_ISI] = { |
|
.name = "dispblk-isi", |
|
.clk_names = (const char *[]){ "disp_axi", "disp_apb", "disp_axi_root", |
|
"disp_apb_root"}, |
|
.num_clks = 4, |
|
.gpc_name = "isi", |
|
.rst_mask = BIT(6) | BIT(7), |
|
.clk_mask = BIT(6) | BIT(7), |
|
}, |
|
}; |
|
|
|
static const struct imx8m_blk_ctrl_data imx8mn_disp_blk_ctl_dev_data = { |
|
.max_reg = 0x84, |
|
.power_notifier_fn = imx8mn_disp_power_notifier, |
|
.domains = imx8mn_disp_blk_ctl_domain_data, |
|
.num_domains = ARRAY_SIZE(imx8mn_disp_blk_ctl_domain_data), |
|
}; |
|
|
|
static int imx8mp_media_power_notifier(struct notifier_block *nb, |
|
unsigned long action, void *data) |
|
{ |
|
struct imx8m_blk_ctrl *bc = container_of(nb, struct imx8m_blk_ctrl, |
|
power_nb); |
|
|
|
if (action != GENPD_NOTIFY_ON && action != GENPD_NOTIFY_PRE_OFF) |
|
return NOTIFY_OK; |
|
|
|
/* Enable bus clock and deassert bus reset */ |
|
regmap_set_bits(bc->regmap, BLK_CLK_EN, BIT(8)); |
|
regmap_set_bits(bc->regmap, BLK_SFT_RSTN, BIT(8)); |
|
|
|
/* |
|
* On power up we have no software backchannel to the GPC to |
|
* wait for the ADB handshake to happen, so we just delay for a |
|
* bit. On power down the GPC driver waits for the handshake. |
|
*/ |
|
if (action == GENPD_NOTIFY_ON) |
|
udelay(5); |
|
|
|
return NOTIFY_OK; |
|
} |
|
|
|
/* |
|
* From i.MX 8M Plus Applications Processor Reference Manual, Rev. 1, |
|
* section 13.2.2, 13.2.3 |
|
* isp-ahb and dwe are not in Figure 13-5. Media BLK_CTRL Clocks |
|
*/ |
|
static const struct imx8m_blk_ctrl_domain_data imx8mp_media_blk_ctl_domain_data[] = { |
|
[IMX8MP_MEDIABLK_PD_MIPI_DSI_1] = { |
|
.name = "mediablk-mipi-dsi-1", |
|
.clk_names = (const char *[]){ "apb", "phy", }, |
|
.num_clks = 2, |
|
.gpc_name = "mipi-dsi1", |
|
.rst_mask = BIT(0) | BIT(1), |
|
.clk_mask = BIT(0) | BIT(1), |
|
.mipi_phy_rst_mask = BIT(17), |
|
}, |
|
[IMX8MP_MEDIABLK_PD_MIPI_CSI2_1] = { |
|
.name = "mediablk-mipi-csi2-1", |
|
.clk_names = (const char *[]){ "apb", "cam1" }, |
|
.num_clks = 2, |
|
.gpc_name = "mipi-csi1", |
|
.rst_mask = BIT(2) | BIT(3), |
|
.clk_mask = BIT(2) | BIT(3), |
|
.mipi_phy_rst_mask = BIT(16), |
|
}, |
|
[IMX8MP_MEDIABLK_PD_LCDIF_1] = { |
|
.name = "mediablk-lcdif-1", |
|
.clk_names = (const char *[]){ "disp1", "apb", "axi", }, |
|
.num_clks = 3, |
|
.gpc_name = "lcdif1", |
|
.rst_mask = BIT(4) | BIT(5) | BIT(23), |
|
.clk_mask = BIT(4) | BIT(5) | BIT(23), |
|
.path_names = (const char *[]){"lcdif-rd", "lcdif-wr"}, |
|
.num_paths = 2, |
|
}, |
|
[IMX8MP_MEDIABLK_PD_ISI] = { |
|
.name = "mediablk-isi", |
|
.clk_names = (const char *[]){ "axi", "apb" }, |
|
.num_clks = 2, |
|
.gpc_name = "isi", |
|
.rst_mask = BIT(6) | BIT(7), |
|
.clk_mask = BIT(6) | BIT(7), |
|
.path_names = (const char *[]){"isi0", "isi1", "isi2"}, |
|
.num_paths = 3, |
|
}, |
|
[IMX8MP_MEDIABLK_PD_MIPI_CSI2_2] = { |
|
.name = "mediablk-mipi-csi2-2", |
|
.clk_names = (const char *[]){ "apb", "cam2" }, |
|
.num_clks = 2, |
|
.gpc_name = "mipi-csi2", |
|
.rst_mask = BIT(9) | BIT(10), |
|
.clk_mask = BIT(9) | BIT(10), |
|
.mipi_phy_rst_mask = BIT(30), |
|
}, |
|
[IMX8MP_MEDIABLK_PD_LCDIF_2] = { |
|
.name = "mediablk-lcdif-2", |
|
.clk_names = (const char *[]){ "disp2", "apb", "axi", }, |
|
.num_clks = 3, |
|
.gpc_name = "lcdif2", |
|
.rst_mask = BIT(11) | BIT(12) | BIT(24), |
|
.clk_mask = BIT(11) | BIT(12) | BIT(24), |
|
.path_names = (const char *[]){"lcdif-rd", "lcdif-wr"}, |
|
.num_paths = 2, |
|
}, |
|
[IMX8MP_MEDIABLK_PD_ISP] = { |
|
.name = "mediablk-isp", |
|
.clk_names = (const char *[]){ "isp", "axi", "apb" }, |
|
.num_clks = 3, |
|
.gpc_name = "isp", |
|
.rst_mask = BIT(16) | BIT(17) | BIT(18), |
|
.clk_mask = BIT(16) | BIT(17) | BIT(18), |
|
.path_names = (const char *[]){"isp0", "isp1"}, |
|
.num_paths = 2, |
|
}, |
|
[IMX8MP_MEDIABLK_PD_DWE] = { |
|
.name = "mediablk-dwe", |
|
.clk_names = (const char *[]){ "axi", "apb" }, |
|
.num_clks = 2, |
|
.gpc_name = "dwe", |
|
.rst_mask = BIT(19) | BIT(20) | BIT(21), |
|
.clk_mask = BIT(19) | BIT(20) | BIT(21), |
|
.path_names = (const char *[]){"dwe"}, |
|
.num_paths = 1, |
|
}, |
|
[IMX8MP_MEDIABLK_PD_MIPI_DSI_2] = { |
|
.name = "mediablk-mipi-dsi-2", |
|
.clk_names = (const char *[]){ "phy", }, |
|
.num_clks = 1, |
|
.gpc_name = "mipi-dsi2", |
|
.rst_mask = BIT(22), |
|
.clk_mask = BIT(22), |
|
.mipi_phy_rst_mask = BIT(29), |
|
}, |
|
}; |
|
|
|
static const struct imx8m_blk_ctrl_data imx8mp_media_blk_ctl_dev_data = { |
|
.max_reg = 0x138, |
|
.power_notifier_fn = imx8mp_media_power_notifier, |
|
.domains = imx8mp_media_blk_ctl_domain_data, |
|
.num_domains = ARRAY_SIZE(imx8mp_media_blk_ctl_domain_data), |
|
}; |
|
|
|
static int imx8mq_vpu_power_notifier(struct notifier_block *nb, |
|
unsigned long action, void *data) |
|
{ |
|
struct imx8m_blk_ctrl *bc = container_of(nb, struct imx8m_blk_ctrl, |
|
power_nb); |
|
|
|
if (action != GENPD_NOTIFY_ON && action != GENPD_NOTIFY_PRE_OFF) |
|
return NOTIFY_OK; |
|
|
|
/* |
|
* The ADB in the VPUMIX domain has no separate reset and clock |
|
* enable bits, but is ungated and reset together with the VPUs. The |
|
* reset and clock enable inputs to the ADB is a logical OR of the |
|
* VPU bits. In order to set the G2 fuse bits, the G2 clock must |
|
* also be enabled. |
|
*/ |
|
regmap_set_bits(bc->regmap, BLK_SFT_RSTN, BIT(0) | BIT(1)); |
|
regmap_set_bits(bc->regmap, BLK_CLK_EN, BIT(0) | BIT(1)); |
|
|
|
if (action == GENPD_NOTIFY_ON) { |
|
/* |
|
* On power up we have no software backchannel to the GPC to |
|
* wait for the ADB handshake to happen, so we just delay for a |
|
* bit. On power down the GPC driver waits for the handshake. |
|
*/ |
|
udelay(5); |
|
|
|
/* set "fuse" bits to enable the VPUs */ |
|
regmap_set_bits(bc->regmap, 0x8, 0xffffffff); |
|
regmap_set_bits(bc->regmap, 0xc, 0xffffffff); |
|
regmap_set_bits(bc->regmap, 0x10, 0xffffffff); |
|
} |
|
|
|
return NOTIFY_OK; |
|
} |
|
|
|
static const struct imx8m_blk_ctrl_domain_data imx8mq_vpu_blk_ctl_domain_data[] = { |
|
[IMX8MQ_VPUBLK_PD_G1] = { |
|
.name = "vpublk-g1", |
|
.clk_names = (const char *[]){ "g1", }, |
|
.num_clks = 1, |
|
.gpc_name = "g1", |
|
.rst_mask = BIT(1), |
|
.clk_mask = BIT(1), |
|
}, |
|
[IMX8MQ_VPUBLK_PD_G2] = { |
|
.name = "vpublk-g2", |
|
.clk_names = (const char *[]){ "g2", }, |
|
.num_clks = 1, |
|
.gpc_name = "g2", |
|
.rst_mask = BIT(0), |
|
.clk_mask = BIT(0), |
|
}, |
|
}; |
|
|
|
static const struct imx8m_blk_ctrl_data imx8mq_vpu_blk_ctl_dev_data = { |
|
.max_reg = 0x14, |
|
.power_notifier_fn = imx8mq_vpu_power_notifier, |
|
.domains = imx8mq_vpu_blk_ctl_domain_data, |
|
.num_domains = ARRAY_SIZE(imx8mq_vpu_blk_ctl_domain_data), |
|
}; |
|
|
|
static const struct of_device_id imx8m_blk_ctrl_of_match[] = { |
|
{ |
|
.compatible = "fsl,imx8mm-vpu-blk-ctrl", |
|
.data = &imx8mm_vpu_blk_ctl_dev_data |
|
}, { |
|
.compatible = "fsl,imx8mm-disp-blk-ctrl", |
|
.data = &imx8mm_disp_blk_ctl_dev_data |
|
}, { |
|
.compatible = "fsl,imx8mn-disp-blk-ctrl", |
|
.data = &imx8mn_disp_blk_ctl_dev_data |
|
}, { |
|
.compatible = "fsl,imx8mp-media-blk-ctrl", |
|
.data = &imx8mp_media_blk_ctl_dev_data |
|
}, { |
|
.compatible = "fsl,imx8mq-vpu-blk-ctrl", |
|
.data = &imx8mq_vpu_blk_ctl_dev_data |
|
}, { |
|
.compatible = "fsl,imx8mp-vpu-blk-ctrl", |
|
.data = &imx8mp_vpu_blk_ctl_dev_data |
|
}, { |
|
/* Sentinel */ |
|
} |
|
}; |
|
MODULE_DEVICE_TABLE(of, imx8m_blk_ctrl_of_match); |
|
|
|
static struct platform_driver imx8m_blk_ctrl_driver = { |
|
.probe = imx8m_blk_ctrl_probe, |
|
.remove = imx8m_blk_ctrl_remove, |
|
.driver = { |
|
.name = "imx8m-blk-ctrl", |
|
.pm = &imx8m_blk_ctrl_pm_ops, |
|
.of_match_table = imx8m_blk_ctrl_of_match, |
|
}, |
|
}; |
|
module_platform_driver(imx8m_blk_ctrl_driver);
|
|
|