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814 lines
19 KiB
814 lines
19 KiB
// SPDX-License-Identifier: GPL-2.0-only |
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/* |
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* Marvell 88SE64xx hardware specific |
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* |
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* Copyright 2007 Red Hat, Inc. |
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* Copyright 2008 Marvell. <[email protected]> |
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* Copyright 2009-2011 Marvell. <[email protected]> |
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*/ |
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|
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#include "mv_sas.h" |
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#include "mv_64xx.h" |
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#include "mv_chips.h" |
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static void mvs_64xx_detect_porttype(struct mvs_info *mvi, int i) |
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{ |
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void __iomem *regs = mvi->regs; |
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u32 reg; |
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struct mvs_phy *phy = &mvi->phy[i]; |
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reg = mr32(MVS_GBL_PORT_TYPE); |
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phy->phy_type &= ~(PORT_TYPE_SAS | PORT_TYPE_SATA); |
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if (reg & MODE_SAS_SATA & (1 << i)) |
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phy->phy_type |= PORT_TYPE_SAS; |
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else |
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phy->phy_type |= PORT_TYPE_SATA; |
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} |
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static void mvs_64xx_enable_xmt(struct mvs_info *mvi, int phy_id) |
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{ |
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void __iomem *regs = mvi->regs; |
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u32 tmp; |
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tmp = mr32(MVS_PCS); |
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if (mvi->chip->n_phy <= MVS_SOC_PORTS) |
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tmp |= 1 << (phy_id + PCS_EN_PORT_XMT_SHIFT); |
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else |
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tmp |= 1 << (phy_id + PCS_EN_PORT_XMT_SHIFT2); |
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mw32(MVS_PCS, tmp); |
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} |
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static void mvs_64xx_phy_hacks(struct mvs_info *mvi) |
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{ |
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void __iomem *regs = mvi->regs; |
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int i; |
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mvs_phy_hacks(mvi); |
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if (!(mvi->flags & MVF_FLAG_SOC)) { |
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for (i = 0; i < MVS_SOC_PORTS; i++) { |
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mvs_write_port_vsr_addr(mvi, i, VSR_PHY_MODE8); |
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mvs_write_port_vsr_data(mvi, i, 0x2F0); |
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} |
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} else { |
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/* disable auto port detection */ |
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mw32(MVS_GBL_PORT_TYPE, 0); |
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for (i = 0; i < mvi->chip->n_phy; i++) { |
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mvs_write_port_vsr_addr(mvi, i, VSR_PHY_MODE7); |
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mvs_write_port_vsr_data(mvi, i, 0x90000000); |
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mvs_write_port_vsr_addr(mvi, i, VSR_PHY_MODE9); |
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mvs_write_port_vsr_data(mvi, i, 0x50f2); |
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mvs_write_port_vsr_addr(mvi, i, VSR_PHY_MODE11); |
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mvs_write_port_vsr_data(mvi, i, 0x0e); |
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} |
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} |
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} |
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static void mvs_64xx_stp_reset(struct mvs_info *mvi, u32 phy_id) |
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{ |
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void __iomem *regs = mvi->regs; |
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u32 reg, tmp; |
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if (!(mvi->flags & MVF_FLAG_SOC)) { |
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if (phy_id < MVS_SOC_PORTS) |
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pci_read_config_dword(mvi->pdev, PCR_PHY_CTL, ®); |
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else |
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pci_read_config_dword(mvi->pdev, PCR_PHY_CTL2, ®); |
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} else |
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reg = mr32(MVS_PHY_CTL); |
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tmp = reg; |
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if (phy_id < MVS_SOC_PORTS) |
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tmp |= (1U << phy_id) << PCTL_LINK_OFFS; |
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else |
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tmp |= (1U << (phy_id - MVS_SOC_PORTS)) << PCTL_LINK_OFFS; |
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if (!(mvi->flags & MVF_FLAG_SOC)) { |
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if (phy_id < MVS_SOC_PORTS) { |
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pci_write_config_dword(mvi->pdev, PCR_PHY_CTL, tmp); |
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mdelay(10); |
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pci_write_config_dword(mvi->pdev, PCR_PHY_CTL, reg); |
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} else { |
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pci_write_config_dword(mvi->pdev, PCR_PHY_CTL2, tmp); |
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mdelay(10); |
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pci_write_config_dword(mvi->pdev, PCR_PHY_CTL2, reg); |
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} |
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} else { |
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mw32(MVS_PHY_CTL, tmp); |
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mdelay(10); |
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mw32(MVS_PHY_CTL, reg); |
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} |
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} |
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static void mvs_64xx_phy_reset(struct mvs_info *mvi, u32 phy_id, int hard) |
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{ |
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u32 tmp; |
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tmp = mvs_read_port_irq_stat(mvi, phy_id); |
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tmp &= ~PHYEV_RDY_CH; |
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mvs_write_port_irq_stat(mvi, phy_id, tmp); |
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tmp = mvs_read_phy_ctl(mvi, phy_id); |
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if (hard == MVS_HARD_RESET) |
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tmp |= PHY_RST_HARD; |
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else if (hard == MVS_SOFT_RESET) |
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tmp |= PHY_RST; |
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mvs_write_phy_ctl(mvi, phy_id, tmp); |
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if (hard) { |
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do { |
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tmp = mvs_read_phy_ctl(mvi, phy_id); |
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} while (tmp & PHY_RST_HARD); |
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} |
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} |
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static void |
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mvs_64xx_clear_srs_irq(struct mvs_info *mvi, u8 reg_set, u8 clear_all) |
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{ |
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void __iomem *regs = mvi->regs; |
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u32 tmp; |
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if (clear_all) { |
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tmp = mr32(MVS_INT_STAT_SRS_0); |
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if (tmp) { |
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printk(KERN_DEBUG "check SRS 0 %08X.\n", tmp); |
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mw32(MVS_INT_STAT_SRS_0, tmp); |
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} |
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} else { |
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tmp = mr32(MVS_INT_STAT_SRS_0); |
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if (tmp & (1 << (reg_set % 32))) { |
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printk(KERN_DEBUG "register set 0x%x was stopped.\n", |
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reg_set); |
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mw32(MVS_INT_STAT_SRS_0, 1 << (reg_set % 32)); |
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} |
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} |
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} |
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static int mvs_64xx_chip_reset(struct mvs_info *mvi) |
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{ |
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void __iomem *regs = mvi->regs; |
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u32 tmp; |
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int i; |
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/* make sure interrupts are masked immediately (paranoia) */ |
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mw32(MVS_GBL_CTL, 0); |
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tmp = mr32(MVS_GBL_CTL); |
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/* Reset Controller */ |
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if (!(tmp & HBA_RST)) { |
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if (mvi->flags & MVF_PHY_PWR_FIX) { |
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pci_read_config_dword(mvi->pdev, PCR_PHY_CTL, &tmp); |
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tmp &= ~PCTL_PWR_OFF; |
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tmp |= PCTL_PHY_DSBL; |
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pci_write_config_dword(mvi->pdev, PCR_PHY_CTL, tmp); |
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pci_read_config_dword(mvi->pdev, PCR_PHY_CTL2, &tmp); |
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tmp &= ~PCTL_PWR_OFF; |
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tmp |= PCTL_PHY_DSBL; |
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pci_write_config_dword(mvi->pdev, PCR_PHY_CTL2, tmp); |
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} |
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} |
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/* make sure interrupts are masked immediately (paranoia) */ |
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mw32(MVS_GBL_CTL, 0); |
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tmp = mr32(MVS_GBL_CTL); |
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/* Reset Controller */ |
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if (!(tmp & HBA_RST)) { |
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/* global reset, incl. COMRESET/H_RESET_N (self-clearing) */ |
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mw32_f(MVS_GBL_CTL, HBA_RST); |
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} |
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/* wait for reset to finish; timeout is just a guess */ |
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i = 1000; |
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while (i-- > 0) { |
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msleep(10); |
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if (!(mr32(MVS_GBL_CTL) & HBA_RST)) |
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break; |
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} |
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if (mr32(MVS_GBL_CTL) & HBA_RST) { |
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dev_printk(KERN_ERR, mvi->dev, "HBA reset failed\n"); |
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return -EBUSY; |
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} |
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return 0; |
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} |
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static void mvs_64xx_phy_disable(struct mvs_info *mvi, u32 phy_id) |
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{ |
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void __iomem *regs = mvi->regs; |
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u32 tmp; |
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if (!(mvi->flags & MVF_FLAG_SOC)) { |
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u32 offs; |
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if (phy_id < 4) |
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offs = PCR_PHY_CTL; |
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else { |
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offs = PCR_PHY_CTL2; |
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phy_id -= 4; |
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} |
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pci_read_config_dword(mvi->pdev, offs, &tmp); |
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tmp |= 1U << (PCTL_PHY_DSBL_OFFS + phy_id); |
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pci_write_config_dword(mvi->pdev, offs, tmp); |
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} else { |
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tmp = mr32(MVS_PHY_CTL); |
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tmp |= 1U << (PCTL_PHY_DSBL_OFFS + phy_id); |
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mw32(MVS_PHY_CTL, tmp); |
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} |
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} |
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static void mvs_64xx_phy_enable(struct mvs_info *mvi, u32 phy_id) |
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{ |
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void __iomem *regs = mvi->regs; |
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u32 tmp; |
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if (!(mvi->flags & MVF_FLAG_SOC)) { |
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u32 offs; |
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if (phy_id < 4) |
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offs = PCR_PHY_CTL; |
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else { |
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offs = PCR_PHY_CTL2; |
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phy_id -= 4; |
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} |
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pci_read_config_dword(mvi->pdev, offs, &tmp); |
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tmp &= ~(1U << (PCTL_PHY_DSBL_OFFS + phy_id)); |
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pci_write_config_dword(mvi->pdev, offs, tmp); |
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} else { |
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tmp = mr32(MVS_PHY_CTL); |
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tmp &= ~(1U << (PCTL_PHY_DSBL_OFFS + phy_id)); |
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mw32(MVS_PHY_CTL, tmp); |
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} |
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} |
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static int mvs_64xx_init(struct mvs_info *mvi) |
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{ |
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void __iomem *regs = mvi->regs; |
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int i; |
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u32 tmp, cctl; |
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if (mvi->pdev && mvi->pdev->revision == 0) |
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mvi->flags |= MVF_PHY_PWR_FIX; |
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if (!(mvi->flags & MVF_FLAG_SOC)) { |
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mvs_show_pcie_usage(mvi); |
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tmp = mvs_64xx_chip_reset(mvi); |
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if (tmp) |
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return tmp; |
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} else { |
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tmp = mr32(MVS_PHY_CTL); |
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tmp &= ~PCTL_PWR_OFF; |
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tmp |= PCTL_PHY_DSBL; |
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mw32(MVS_PHY_CTL, tmp); |
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} |
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/* Init Chip */ |
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/* make sure RST is set; HBA_RST /should/ have done that for us */ |
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cctl = mr32(MVS_CTL) & 0xFFFF; |
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if (cctl & CCTL_RST) |
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cctl &= ~CCTL_RST; |
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else |
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mw32_f(MVS_CTL, cctl | CCTL_RST); |
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if (!(mvi->flags & MVF_FLAG_SOC)) { |
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/* write to device control _AND_ device status register */ |
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pci_read_config_dword(mvi->pdev, PCR_DEV_CTRL, &tmp); |
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tmp &= ~PRD_REQ_MASK; |
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tmp |= PRD_REQ_SIZE; |
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pci_write_config_dword(mvi->pdev, PCR_DEV_CTRL, tmp); |
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pci_read_config_dword(mvi->pdev, PCR_PHY_CTL, &tmp); |
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tmp &= ~PCTL_PWR_OFF; |
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tmp &= ~PCTL_PHY_DSBL; |
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pci_write_config_dword(mvi->pdev, PCR_PHY_CTL, tmp); |
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pci_read_config_dword(mvi->pdev, PCR_PHY_CTL2, &tmp); |
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tmp &= PCTL_PWR_OFF; |
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tmp &= ~PCTL_PHY_DSBL; |
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pci_write_config_dword(mvi->pdev, PCR_PHY_CTL2, tmp); |
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} else { |
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tmp = mr32(MVS_PHY_CTL); |
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tmp &= ~PCTL_PWR_OFF; |
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tmp |= PCTL_COM_ON; |
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tmp &= ~PCTL_PHY_DSBL; |
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tmp |= PCTL_LINK_RST; |
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mw32(MVS_PHY_CTL, tmp); |
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msleep(100); |
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tmp &= ~PCTL_LINK_RST; |
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mw32(MVS_PHY_CTL, tmp); |
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msleep(100); |
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} |
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/* reset control */ |
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mw32(MVS_PCS, 0); /* MVS_PCS */ |
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/* init phys */ |
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mvs_64xx_phy_hacks(mvi); |
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tmp = mvs_cr32(mvi, CMD_PHY_MODE_21); |
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tmp &= 0x0000ffff; |
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tmp |= 0x00fa0000; |
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mvs_cw32(mvi, CMD_PHY_MODE_21, tmp); |
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/* enable auto port detection */ |
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mw32(MVS_GBL_PORT_TYPE, MODE_AUTO_DET_EN); |
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mw32(MVS_CMD_LIST_LO, mvi->slot_dma); |
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mw32(MVS_CMD_LIST_HI, (mvi->slot_dma >> 16) >> 16); |
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mw32(MVS_RX_FIS_LO, mvi->rx_fis_dma); |
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mw32(MVS_RX_FIS_HI, (mvi->rx_fis_dma >> 16) >> 16); |
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mw32(MVS_TX_CFG, MVS_CHIP_SLOT_SZ); |
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mw32(MVS_TX_LO, mvi->tx_dma); |
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mw32(MVS_TX_HI, (mvi->tx_dma >> 16) >> 16); |
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mw32(MVS_RX_CFG, MVS_RX_RING_SZ); |
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mw32(MVS_RX_LO, mvi->rx_dma); |
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mw32(MVS_RX_HI, (mvi->rx_dma >> 16) >> 16); |
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for (i = 0; i < mvi->chip->n_phy; i++) { |
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/* set phy local SAS address */ |
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/* should set little endian SAS address to 64xx chip */ |
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mvs_set_sas_addr(mvi, i, PHYR_ADDR_LO, PHYR_ADDR_HI, |
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cpu_to_be64(mvi->phy[i].dev_sas_addr)); |
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mvs_64xx_enable_xmt(mvi, i); |
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mvs_64xx_phy_reset(mvi, i, MVS_HARD_RESET); |
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msleep(500); |
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mvs_64xx_detect_porttype(mvi, i); |
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} |
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if (mvi->flags & MVF_FLAG_SOC) { |
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/* set select registers */ |
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writel(0x0E008000, regs + 0x000); |
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writel(0x59000008, regs + 0x004); |
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writel(0x20, regs + 0x008); |
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writel(0x20, regs + 0x00c); |
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writel(0x20, regs + 0x010); |
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writel(0x20, regs + 0x014); |
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writel(0x20, regs + 0x018); |
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writel(0x20, regs + 0x01c); |
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} |
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for (i = 0; i < mvi->chip->n_phy; i++) { |
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/* clear phy int status */ |
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tmp = mvs_read_port_irq_stat(mvi, i); |
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tmp &= ~PHYEV_SIG_FIS; |
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mvs_write_port_irq_stat(mvi, i, tmp); |
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/* set phy int mask */ |
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tmp = PHYEV_RDY_CH | PHYEV_BROAD_CH | PHYEV_UNASSOC_FIS | |
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PHYEV_ID_DONE | PHYEV_DCDR_ERR | PHYEV_CRC_ERR | |
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PHYEV_DEC_ERR; |
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mvs_write_port_irq_mask(mvi, i, tmp); |
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msleep(100); |
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mvs_update_phyinfo(mvi, i, 1); |
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} |
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/* little endian for open address and command table, etc. */ |
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cctl = mr32(MVS_CTL); |
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cctl |= CCTL_ENDIAN_CMD; |
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cctl |= CCTL_ENDIAN_DATA; |
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cctl &= ~CCTL_ENDIAN_OPEN; |
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cctl |= CCTL_ENDIAN_RSP; |
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mw32_f(MVS_CTL, cctl); |
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/* reset CMD queue */ |
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tmp = mr32(MVS_PCS); |
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tmp |= PCS_CMD_RST; |
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tmp &= ~PCS_SELF_CLEAR; |
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mw32(MVS_PCS, tmp); |
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/* |
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* the max count is 0x1ff, while our max slot is 0x200, |
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* it will make count 0. |
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*/ |
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tmp = 0; |
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if (MVS_CHIP_SLOT_SZ > 0x1ff) |
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mw32(MVS_INT_COAL, 0x1ff | COAL_EN); |
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else |
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mw32(MVS_INT_COAL, MVS_CHIP_SLOT_SZ | COAL_EN); |
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tmp = 0x10000 | interrupt_coalescing; |
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mw32(MVS_INT_COAL_TMOUT, tmp); |
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/* ladies and gentlemen, start your engines */ |
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mw32(MVS_TX_CFG, 0); |
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mw32(MVS_TX_CFG, MVS_CHIP_SLOT_SZ | TX_EN); |
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mw32(MVS_RX_CFG, MVS_RX_RING_SZ | RX_EN); |
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/* enable CMD/CMPL_Q/RESP mode */ |
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mw32(MVS_PCS, PCS_SATA_RETRY | PCS_FIS_RX_EN | |
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PCS_CMD_EN | PCS_CMD_STOP_ERR); |
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/* enable completion queue interrupt */ |
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tmp = (CINT_PORT_MASK | CINT_DONE | CINT_MEM | CINT_SRS | CINT_CI_STOP | |
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CINT_DMA_PCIE); |
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mw32(MVS_INT_MASK, tmp); |
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/* Enable SRS interrupt */ |
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mw32(MVS_INT_MASK_SRS_0, 0xFFFF); |
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return 0; |
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} |
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static int mvs_64xx_ioremap(struct mvs_info *mvi) |
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{ |
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if (!mvs_ioremap(mvi, 4, 2)) |
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return 0; |
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return -1; |
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} |
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static void mvs_64xx_iounmap(struct mvs_info *mvi) |
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{ |
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mvs_iounmap(mvi->regs); |
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mvs_iounmap(mvi->regs_ex); |
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} |
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static void mvs_64xx_interrupt_enable(struct mvs_info *mvi) |
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{ |
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void __iomem *regs = mvi->regs; |
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u32 tmp; |
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tmp = mr32(MVS_GBL_CTL); |
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mw32(MVS_GBL_CTL, tmp | INT_EN); |
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} |
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static void mvs_64xx_interrupt_disable(struct mvs_info *mvi) |
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{ |
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void __iomem *regs = mvi->regs; |
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u32 tmp; |
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tmp = mr32(MVS_GBL_CTL); |
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mw32(MVS_GBL_CTL, tmp & ~INT_EN); |
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} |
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static u32 mvs_64xx_isr_status(struct mvs_info *mvi, int irq) |
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{ |
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void __iomem *regs = mvi->regs; |
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u32 stat; |
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if (!(mvi->flags & MVF_FLAG_SOC)) { |
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stat = mr32(MVS_GBL_INT_STAT); |
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if (stat == 0 || stat == 0xffffffff) |
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return 0; |
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} else |
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stat = 1; |
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return stat; |
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} |
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static irqreturn_t mvs_64xx_isr(struct mvs_info *mvi, int irq, u32 stat) |
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{ |
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void __iomem *regs = mvi->regs; |
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/* clear CMD_CMPLT ASAP */ |
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mw32_f(MVS_INT_STAT, CINT_DONE); |
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spin_lock(&mvi->lock); |
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mvs_int_full(mvi); |
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spin_unlock(&mvi->lock); |
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return IRQ_HANDLED; |
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} |
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static void mvs_64xx_command_active(struct mvs_info *mvi, u32 slot_idx) |
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{ |
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u32 tmp; |
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mvs_cw32(mvi, 0x40 + (slot_idx >> 3), 1 << (slot_idx % 32)); |
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mvs_cw32(mvi, 0x00 + (slot_idx >> 3), 1 << (slot_idx % 32)); |
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do { |
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tmp = mvs_cr32(mvi, 0x00 + (slot_idx >> 3)); |
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} while (tmp & 1 << (slot_idx % 32)); |
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do { |
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tmp = mvs_cr32(mvi, 0x40 + (slot_idx >> 3)); |
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} while (tmp & 1 << (slot_idx % 32)); |
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} |
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static void mvs_64xx_issue_stop(struct mvs_info *mvi, enum mvs_port_type type, |
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u32 tfs) |
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{ |
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void __iomem *regs = mvi->regs; |
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u32 tmp; |
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if (type == PORT_TYPE_SATA) { |
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tmp = mr32(MVS_INT_STAT_SRS_0) | (1U << tfs); |
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mw32(MVS_INT_STAT_SRS_0, tmp); |
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} |
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mw32(MVS_INT_STAT, CINT_CI_STOP); |
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tmp = mr32(MVS_PCS) | 0xFF00; |
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mw32(MVS_PCS, tmp); |
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} |
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static void mvs_64xx_free_reg_set(struct mvs_info *mvi, u8 *tfs) |
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{ |
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void __iomem *regs = mvi->regs; |
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u32 tmp, offs; |
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if (*tfs == MVS_ID_NOT_MAPPED) |
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return; |
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offs = 1U << ((*tfs & 0x0f) + PCS_EN_SATA_REG_SHIFT); |
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if (*tfs < 16) { |
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tmp = mr32(MVS_PCS); |
|
mw32(MVS_PCS, tmp & ~offs); |
|
} else { |
|
tmp = mr32(MVS_CTL); |
|
mw32(MVS_CTL, tmp & ~offs); |
|
} |
|
|
|
tmp = mr32(MVS_INT_STAT_SRS_0) & (1U << *tfs); |
|
if (tmp) |
|
mw32(MVS_INT_STAT_SRS_0, tmp); |
|
|
|
*tfs = MVS_ID_NOT_MAPPED; |
|
return; |
|
} |
|
|
|
static u8 mvs_64xx_assign_reg_set(struct mvs_info *mvi, u8 *tfs) |
|
{ |
|
int i; |
|
u32 tmp, offs; |
|
void __iomem *regs = mvi->regs; |
|
|
|
if (*tfs != MVS_ID_NOT_MAPPED) |
|
return 0; |
|
|
|
tmp = mr32(MVS_PCS); |
|
|
|
for (i = 0; i < mvi->chip->srs_sz; i++) { |
|
if (i == 16) |
|
tmp = mr32(MVS_CTL); |
|
offs = 1U << ((i & 0x0f) + PCS_EN_SATA_REG_SHIFT); |
|
if (!(tmp & offs)) { |
|
*tfs = i; |
|
|
|
if (i < 16) |
|
mw32(MVS_PCS, tmp | offs); |
|
else |
|
mw32(MVS_CTL, tmp | offs); |
|
tmp = mr32(MVS_INT_STAT_SRS_0) & (1U << i); |
|
if (tmp) |
|
mw32(MVS_INT_STAT_SRS_0, tmp); |
|
return 0; |
|
} |
|
} |
|
return MVS_ID_NOT_MAPPED; |
|
} |
|
|
|
static void mvs_64xx_make_prd(struct scatterlist *scatter, int nr, void *prd) |
|
{ |
|
int i; |
|
struct scatterlist *sg; |
|
struct mvs_prd *buf_prd = prd; |
|
for_each_sg(scatter, sg, nr, i) { |
|
buf_prd->addr = cpu_to_le64(sg_dma_address(sg)); |
|
buf_prd->len = cpu_to_le32(sg_dma_len(sg)); |
|
buf_prd++; |
|
} |
|
} |
|
|
|
static int mvs_64xx_oob_done(struct mvs_info *mvi, int i) |
|
{ |
|
u32 phy_st; |
|
mvs_write_port_cfg_addr(mvi, i, |
|
PHYR_PHY_STAT); |
|
phy_st = mvs_read_port_cfg_data(mvi, i); |
|
if (phy_st & PHY_OOB_DTCTD) |
|
return 1; |
|
return 0; |
|
} |
|
|
|
static void mvs_64xx_fix_phy_info(struct mvs_info *mvi, int i, |
|
struct sas_identify_frame *id) |
|
|
|
{ |
|
struct mvs_phy *phy = &mvi->phy[i]; |
|
struct asd_sas_phy *sas_phy = &phy->sas_phy; |
|
|
|
sas_phy->linkrate = |
|
(phy->phy_status & PHY_NEG_SPP_PHYS_LINK_RATE_MASK) >> |
|
PHY_NEG_SPP_PHYS_LINK_RATE_MASK_OFFSET; |
|
|
|
phy->minimum_linkrate = |
|
(phy->phy_status & |
|
PHY_MIN_SPP_PHYS_LINK_RATE_MASK) >> 8; |
|
phy->maximum_linkrate = |
|
(phy->phy_status & |
|
PHY_MAX_SPP_PHYS_LINK_RATE_MASK) >> 12; |
|
|
|
mvs_write_port_cfg_addr(mvi, i, PHYR_IDENTIFY); |
|
phy->dev_info = mvs_read_port_cfg_data(mvi, i); |
|
|
|
mvs_write_port_cfg_addr(mvi, i, PHYR_ATT_DEV_INFO); |
|
phy->att_dev_info = mvs_read_port_cfg_data(mvi, i); |
|
|
|
mvs_write_port_cfg_addr(mvi, i, PHYR_ATT_ADDR_HI); |
|
phy->att_dev_sas_addr = |
|
(u64) mvs_read_port_cfg_data(mvi, i) << 32; |
|
mvs_write_port_cfg_addr(mvi, i, PHYR_ATT_ADDR_LO); |
|
phy->att_dev_sas_addr |= mvs_read_port_cfg_data(mvi, i); |
|
phy->att_dev_sas_addr = SAS_ADDR(&phy->att_dev_sas_addr); |
|
} |
|
|
|
static void mvs_64xx_phy_work_around(struct mvs_info *mvi, int i) |
|
{ |
|
u32 tmp; |
|
struct mvs_phy *phy = &mvi->phy[i]; |
|
mvs_write_port_vsr_addr(mvi, i, VSR_PHY_MODE6); |
|
tmp = mvs_read_port_vsr_data(mvi, i); |
|
if (((phy->phy_status & PHY_NEG_SPP_PHYS_LINK_RATE_MASK) >> |
|
PHY_NEG_SPP_PHYS_LINK_RATE_MASK_OFFSET) == |
|
SAS_LINK_RATE_1_5_GBPS) |
|
tmp &= ~PHY_MODE6_LATECLK; |
|
else |
|
tmp |= PHY_MODE6_LATECLK; |
|
mvs_write_port_vsr_data(mvi, i, tmp); |
|
} |
|
|
|
static void mvs_64xx_phy_set_link_rate(struct mvs_info *mvi, u32 phy_id, |
|
struct sas_phy_linkrates *rates) |
|
{ |
|
u32 lrmin = 0, lrmax = 0; |
|
u32 tmp; |
|
|
|
tmp = mvs_read_phy_ctl(mvi, phy_id); |
|
lrmin = (rates->minimum_linkrate << 8); |
|
lrmax = (rates->maximum_linkrate << 12); |
|
|
|
if (lrmin) { |
|
tmp &= ~(0xf << 8); |
|
tmp |= lrmin; |
|
} |
|
if (lrmax) { |
|
tmp &= ~(0xf << 12); |
|
tmp |= lrmax; |
|
} |
|
mvs_write_phy_ctl(mvi, phy_id, tmp); |
|
mvs_64xx_phy_reset(mvi, phy_id, MVS_HARD_RESET); |
|
} |
|
|
|
static void mvs_64xx_clear_active_cmds(struct mvs_info *mvi) |
|
{ |
|
u32 tmp; |
|
void __iomem *regs = mvi->regs; |
|
tmp = mr32(MVS_PCS); |
|
mw32(MVS_PCS, tmp & 0xFFFF); |
|
mw32(MVS_PCS, tmp); |
|
tmp = mr32(MVS_CTL); |
|
mw32(MVS_CTL, tmp & 0xFFFF); |
|
mw32(MVS_CTL, tmp); |
|
} |
|
|
|
|
|
static u32 mvs_64xx_spi_read_data(struct mvs_info *mvi) |
|
{ |
|
void __iomem *regs = mvi->regs_ex; |
|
return ior32(SPI_DATA_REG_64XX); |
|
} |
|
|
|
static void mvs_64xx_spi_write_data(struct mvs_info *mvi, u32 data) |
|
{ |
|
void __iomem *regs = mvi->regs_ex; |
|
|
|
iow32(SPI_DATA_REG_64XX, data); |
|
} |
|
|
|
|
|
static int mvs_64xx_spi_buildcmd(struct mvs_info *mvi, |
|
u32 *dwCmd, |
|
u8 cmd, |
|
u8 read, |
|
u8 length, |
|
u32 addr |
|
) |
|
{ |
|
u32 dwTmp; |
|
|
|
dwTmp = ((u32)cmd << 24) | ((u32)length << 19); |
|
if (read) |
|
dwTmp |= 1U<<23; |
|
|
|
if (addr != MV_MAX_U32) { |
|
dwTmp |= 1U<<22; |
|
dwTmp |= (addr & 0x0003FFFF); |
|
} |
|
|
|
*dwCmd = dwTmp; |
|
return 0; |
|
} |
|
|
|
|
|
static int mvs_64xx_spi_issuecmd(struct mvs_info *mvi, u32 cmd) |
|
{ |
|
void __iomem *regs = mvi->regs_ex; |
|
int retry; |
|
|
|
for (retry = 0; retry < 1; retry++) { |
|
iow32(SPI_CTRL_REG_64XX, SPI_CTRL_VENDOR_ENABLE); |
|
iow32(SPI_CMD_REG_64XX, cmd); |
|
iow32(SPI_CTRL_REG_64XX, |
|
SPI_CTRL_VENDOR_ENABLE | SPI_CTRL_SPISTART); |
|
} |
|
|
|
return 0; |
|
} |
|
|
|
static int mvs_64xx_spi_waitdataready(struct mvs_info *mvi, u32 timeout) |
|
{ |
|
void __iomem *regs = mvi->regs_ex; |
|
u32 i, dwTmp; |
|
|
|
for (i = 0; i < timeout; i++) { |
|
dwTmp = ior32(SPI_CTRL_REG_64XX); |
|
if (!(dwTmp & SPI_CTRL_SPISTART)) |
|
return 0; |
|
msleep(10); |
|
} |
|
|
|
return -1; |
|
} |
|
|
|
static void mvs_64xx_fix_dma(struct mvs_info *mvi, u32 phy_mask, |
|
int buf_len, int from, void *prd) |
|
{ |
|
int i; |
|
struct mvs_prd *buf_prd = prd; |
|
dma_addr_t buf_dma = mvi->bulk_buffer_dma; |
|
|
|
buf_prd += from; |
|
for (i = 0; i < MAX_SG_ENTRY - from; i++) { |
|
buf_prd->addr = cpu_to_le64(buf_dma); |
|
buf_prd->len = cpu_to_le32(buf_len); |
|
++buf_prd; |
|
} |
|
} |
|
|
|
static void mvs_64xx_tune_interrupt(struct mvs_info *mvi, u32 time) |
|
{ |
|
void __iomem *regs = mvi->regs; |
|
u32 tmp = 0; |
|
/* |
|
* the max count is 0x1ff, while our max slot is 0x200, |
|
* it will make count 0. |
|
*/ |
|
if (time == 0) { |
|
mw32(MVS_INT_COAL, 0); |
|
mw32(MVS_INT_COAL_TMOUT, 0x10000); |
|
} else { |
|
if (MVS_CHIP_SLOT_SZ > 0x1ff) |
|
mw32(MVS_INT_COAL, 0x1ff|COAL_EN); |
|
else |
|
mw32(MVS_INT_COAL, MVS_CHIP_SLOT_SZ|COAL_EN); |
|
|
|
tmp = 0x10000 | time; |
|
mw32(MVS_INT_COAL_TMOUT, tmp); |
|
} |
|
} |
|
|
|
const struct mvs_dispatch mvs_64xx_dispatch = { |
|
"mv64xx", |
|
mvs_64xx_init, |
|
NULL, |
|
mvs_64xx_ioremap, |
|
mvs_64xx_iounmap, |
|
mvs_64xx_isr, |
|
mvs_64xx_isr_status, |
|
mvs_64xx_interrupt_enable, |
|
mvs_64xx_interrupt_disable, |
|
mvs_read_phy_ctl, |
|
mvs_write_phy_ctl, |
|
mvs_read_port_cfg_data, |
|
mvs_write_port_cfg_data, |
|
mvs_write_port_cfg_addr, |
|
mvs_read_port_vsr_data, |
|
mvs_write_port_vsr_data, |
|
mvs_write_port_vsr_addr, |
|
mvs_read_port_irq_stat, |
|
mvs_write_port_irq_stat, |
|
mvs_read_port_irq_mask, |
|
mvs_write_port_irq_mask, |
|
mvs_64xx_command_active, |
|
mvs_64xx_clear_srs_irq, |
|
mvs_64xx_issue_stop, |
|
mvs_start_delivery, |
|
mvs_rx_update, |
|
mvs_int_full, |
|
mvs_64xx_assign_reg_set, |
|
mvs_64xx_free_reg_set, |
|
mvs_get_prd_size, |
|
mvs_get_prd_count, |
|
mvs_64xx_make_prd, |
|
mvs_64xx_detect_porttype, |
|
mvs_64xx_oob_done, |
|
mvs_64xx_fix_phy_info, |
|
mvs_64xx_phy_work_around, |
|
mvs_64xx_phy_set_link_rate, |
|
mvs_hw_max_link_rate, |
|
mvs_64xx_phy_disable, |
|
mvs_64xx_phy_enable, |
|
mvs_64xx_phy_reset, |
|
mvs_64xx_stp_reset, |
|
mvs_64xx_clear_active_cmds, |
|
mvs_64xx_spi_read_data, |
|
mvs_64xx_spi_write_data, |
|
mvs_64xx_spi_buildcmd, |
|
mvs_64xx_spi_issuecmd, |
|
mvs_64xx_spi_waitdataready, |
|
mvs_64xx_fix_dma, |
|
mvs_64xx_tune_interrupt, |
|
NULL, |
|
}; |
|
|
|
|