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259 lines
6.5 KiB
259 lines
6.5 KiB
// SPDX-License-Identifier: GPL-2.0-only |
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/* |
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* Real time clocks driver for MStar/SigmaStar ARMv7 SoCs. |
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* Based on "Real Time Clock driver for msb252x." that was contained |
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* in various MStar kernels. |
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* |
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* (C) 2019 Daniel Palmer |
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* (C) 2021 Romain Perier |
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*/ |
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#include <linux/clk.h> |
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#include <linux/delay.h> |
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#include <linux/io.h> |
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#include <linux/module.h> |
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#include <linux/mod_devicetable.h> |
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#include <linux/platform_device.h> |
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#include <linux/rtc.h> |
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/* Registers */ |
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#define REG_RTC_CTRL 0x00 |
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#define REG_RTC_FREQ_CW_L 0x04 |
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#define REG_RTC_FREQ_CW_H 0x08 |
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#define REG_RTC_LOAD_VAL_L 0x0C |
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#define REG_RTC_LOAD_VAL_H 0x10 |
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#define REG_RTC_MATCH_VAL_L 0x14 |
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#define REG_RTC_MATCH_VAL_H 0x18 |
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#define REG_RTC_STATUS_INT 0x1C |
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#define REG_RTC_CNT_VAL_L 0x20 |
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#define REG_RTC_CNT_VAL_H 0x24 |
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/* Control bits for REG_RTC_CTRL */ |
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#define SOFT_RSTZ_BIT BIT(0) |
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#define CNT_EN_BIT BIT(1) |
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#define WRAP_EN_BIT BIT(2) |
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#define LOAD_EN_BIT BIT(3) |
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#define READ_EN_BIT BIT(4) |
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#define INT_MASK_BIT BIT(5) |
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#define INT_FORCE_BIT BIT(6) |
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#define INT_CLEAR_BIT BIT(7) |
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/* Control bits for REG_RTC_STATUS_INT */ |
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#define RAW_INT_BIT BIT(0) |
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#define ALM_INT_BIT BIT(1) |
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struct msc313_rtc { |
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struct rtc_device *rtc_dev; |
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void __iomem *rtc_base; |
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}; |
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static int msc313_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alarm) |
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{ |
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struct msc313_rtc *priv = dev_get_drvdata(dev); |
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unsigned long seconds; |
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seconds = readw(priv->rtc_base + REG_RTC_MATCH_VAL_L) |
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| ((unsigned long)readw(priv->rtc_base + REG_RTC_MATCH_VAL_H) << 16); |
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rtc_time64_to_tm(seconds, &alarm->time); |
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if (!(readw(priv->rtc_base + REG_RTC_CTRL) & INT_MASK_BIT)) |
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alarm->enabled = 1; |
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return 0; |
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} |
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static int msc313_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled) |
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{ |
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struct msc313_rtc *priv = dev_get_drvdata(dev); |
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u16 reg; |
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reg = readw(priv->rtc_base + REG_RTC_CTRL); |
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if (enabled) |
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reg &= ~INT_MASK_BIT; |
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else |
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reg |= INT_MASK_BIT; |
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writew(reg, priv->rtc_base + REG_RTC_CTRL); |
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return 0; |
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} |
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static int msc313_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alarm) |
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{ |
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struct msc313_rtc *priv = dev_get_drvdata(dev); |
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unsigned long seconds; |
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seconds = rtc_tm_to_time64(&alarm->time); |
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writew((seconds & 0xFFFF), priv->rtc_base + REG_RTC_MATCH_VAL_L); |
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writew((seconds >> 16) & 0xFFFF, priv->rtc_base + REG_RTC_MATCH_VAL_H); |
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msc313_rtc_alarm_irq_enable(dev, alarm->enabled); |
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return 0; |
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} |
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static bool msc313_rtc_get_enabled(struct msc313_rtc *priv) |
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{ |
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return readw(priv->rtc_base + REG_RTC_CTRL) & CNT_EN_BIT; |
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} |
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static void msc313_rtc_set_enabled(struct msc313_rtc *priv) |
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{ |
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u16 reg; |
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reg = readw(priv->rtc_base + REG_RTC_CTRL); |
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reg |= CNT_EN_BIT; |
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writew(reg, priv->rtc_base + REG_RTC_CTRL); |
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} |
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static int msc313_rtc_read_time(struct device *dev, struct rtc_time *tm) |
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{ |
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struct msc313_rtc *priv = dev_get_drvdata(dev); |
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u32 seconds; |
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u16 reg; |
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if (!msc313_rtc_get_enabled(priv)) |
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return -EINVAL; |
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reg = readw(priv->rtc_base + REG_RTC_CTRL); |
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writew(reg | READ_EN_BIT, priv->rtc_base + REG_RTC_CTRL); |
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/* Wait for HW latch done */ |
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while (readw(priv->rtc_base + REG_RTC_CTRL) & READ_EN_BIT) |
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udelay(1); |
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seconds = readw(priv->rtc_base + REG_RTC_CNT_VAL_L) |
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| ((unsigned long)readw(priv->rtc_base + REG_RTC_CNT_VAL_H) << 16); |
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rtc_time64_to_tm(seconds, tm); |
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return 0; |
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} |
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static int msc313_rtc_set_time(struct device *dev, struct rtc_time *tm) |
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{ |
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struct msc313_rtc *priv = dev_get_drvdata(dev); |
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unsigned long seconds; |
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u16 reg; |
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seconds = rtc_tm_to_time64(tm); |
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writew(seconds & 0xFFFF, priv->rtc_base + REG_RTC_LOAD_VAL_L); |
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writew((seconds >> 16) & 0xFFFF, priv->rtc_base + REG_RTC_LOAD_VAL_H); |
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/* Enable load for loading value into internal RTC counter */ |
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reg = readw(priv->rtc_base + REG_RTC_CTRL); |
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writew(reg | LOAD_EN_BIT, priv->rtc_base + REG_RTC_CTRL); |
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/* Wait for HW latch done */ |
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while (readw(priv->rtc_base + REG_RTC_CTRL) & LOAD_EN_BIT) |
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udelay(1); |
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msc313_rtc_set_enabled(priv); |
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return 0; |
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} |
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static const struct rtc_class_ops msc313_rtc_ops = { |
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.read_time = msc313_rtc_read_time, |
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.set_time = msc313_rtc_set_time, |
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.read_alarm = msc313_rtc_read_alarm, |
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.set_alarm = msc313_rtc_set_alarm, |
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.alarm_irq_enable = msc313_rtc_alarm_irq_enable, |
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}; |
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static irqreturn_t msc313_rtc_interrupt(s32 irq, void *dev_id) |
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{ |
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struct msc313_rtc *priv = dev_get_drvdata(dev_id); |
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u16 reg; |
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reg = readw(priv->rtc_base + REG_RTC_STATUS_INT); |
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if (!(reg & ALM_INT_BIT)) |
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return IRQ_NONE; |
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reg = readw(priv->rtc_base + REG_RTC_CTRL); |
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reg |= INT_CLEAR_BIT; |
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reg &= ~INT_FORCE_BIT; |
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writew(reg, priv->rtc_base + REG_RTC_CTRL); |
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rtc_update_irq(priv->rtc_dev, 1, RTC_IRQF | RTC_AF); |
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return IRQ_HANDLED; |
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} |
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static int msc313_rtc_probe(struct platform_device *pdev) |
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{ |
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struct device *dev = &pdev->dev; |
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struct msc313_rtc *priv; |
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unsigned long rate; |
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struct clk *clk; |
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int ret; |
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int irq; |
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priv = devm_kzalloc(&pdev->dev, sizeof(struct msc313_rtc), GFP_KERNEL); |
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if (!priv) |
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return -ENOMEM; |
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priv->rtc_base = devm_platform_ioremap_resource(pdev, 0); |
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if (IS_ERR(priv->rtc_base)) |
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return PTR_ERR(priv->rtc_base); |
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irq = platform_get_irq(pdev, 0); |
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if (irq < 0) |
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return -EINVAL; |
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priv->rtc_dev = devm_rtc_allocate_device(dev); |
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if (IS_ERR(priv->rtc_dev)) |
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return PTR_ERR(priv->rtc_dev); |
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priv->rtc_dev->ops = &msc313_rtc_ops; |
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priv->rtc_dev->range_max = U32_MAX; |
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ret = devm_request_irq(dev, irq, msc313_rtc_interrupt, IRQF_SHARED, |
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dev_name(&pdev->dev), &pdev->dev); |
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if (ret) { |
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dev_err(dev, "Could not request IRQ\n"); |
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return ret; |
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} |
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clk = devm_clk_get(dev, NULL); |
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if (IS_ERR(clk)) { |
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dev_err(dev, "No input reference clock\n"); |
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return PTR_ERR(clk); |
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} |
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ret = clk_prepare_enable(clk); |
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if (ret) { |
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dev_err(dev, "Failed to enable the reference clock, %d\n", ret); |
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return ret; |
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} |
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ret = devm_add_action_or_reset(dev, (void (*) (void *))clk_disable_unprepare, clk); |
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if (ret) |
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return ret; |
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rate = clk_get_rate(clk); |
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writew(rate & 0xFFFF, priv->rtc_base + REG_RTC_FREQ_CW_L); |
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writew((rate >> 16) & 0xFFFF, priv->rtc_base + REG_RTC_FREQ_CW_H); |
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platform_set_drvdata(pdev, priv); |
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return devm_rtc_register_device(priv->rtc_dev); |
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} |
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static const struct of_device_id msc313_rtc_of_match_table[] = { |
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{ .compatible = "mstar,msc313-rtc" }, |
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{ } |
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}; |
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MODULE_DEVICE_TABLE(of, msc313_rtc_of_match_table); |
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static struct platform_driver msc313_rtc_driver = { |
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.probe = msc313_rtc_probe, |
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.driver = { |
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.name = "msc313-rtc", |
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.of_match_table = msc313_rtc_of_match_table, |
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}, |
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}; |
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module_platform_driver(msc313_rtc_driver); |
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MODULE_AUTHOR("Daniel Palmer <[email protected]>"); |
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MODULE_AUTHOR("Romain Perier <[email protected]>"); |
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MODULE_DESCRIPTION("MStar RTC Driver"); |
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MODULE_LICENSE("GPL v2");
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